Design and Optimization of Ultra-Small Transistors (DOUST)

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Related Publications

  1. H. T. Zhou, X. Zhou, and F. Benistant, "An Explicit Compact Model for High-Voltage LDMOS," International Conference on Solid State Devices and Materials (SSDM2013), Fukuoka, Japan, Sep. 2013, Poster PS-14-4.

    2.  
  2. S. B. Chiah, X. Zhou, and L. Yuan, "Compact Zero-Temperature Coefficient Modeling Approach for MOSFETs Based on Unified Regional Modeling of Surface Potential," IEEE Trans. Electron Devices, Vol. 60, No. 7, pp. 2164-2170, Jul. 2013. Download PDF

    3.  
  3. H. T. Zhou, X. Zhou, and F. Benistant, "An Analytical DC Model for High-Voltage LDMOS," Proc. of the 7th International Conference on Materials for Advanced Technologies (ICMAT2013), Symposium Y: Reliability and Variability of Devices for Circuits and Systems [RV-DCS], Singapore, July 2013, Paper Y6-5.

    4.  
  4. X. Zhou, J. B. Zhang, B. Syamal, Z. M. Zhu, H. T. Zhou, and S. B. Chiah, "Top-down Drift-diffusion versus Bottom-up Quasi-ballistic Formalism in Device Compact Modeling," (Keynote), Proc. of the 20th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2013), Gdynia, Poland, Jun. 2013, p. 53.

    5.  
  5. X. Zhou, J. B. Zhang, B. Syamal, Z. M. Zhu, and L. Yuan, "A Scalable Compact Model for Generic HEMTs in III-V/Si Co-integrated Hybrid Design," (Invited Paper), Proc. of the 9th International Conference on Electron Devices and Solid State Circuits (EDSSC2013), Hong Kong, Jun. 2013, paper 299.

    6.  
  6. X. Zhou, J. B. Zhang, B. Syamal, S. B. Chiah, H. T. Zhou, and L. Yuan, "Unified Regional Modeling of GaN HEMTs with the 2DEG and DD Formalism," (Invited Paper), Proc. of the 11th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2012), Xi'an, China, Oct. 2012, paper S21_01.

    7.  
  7. X. Zhou, S. B. Chiah, and L. Yuan, "A Simplified Model for Dynamic Depletion in Doped UTB-SOI/DG-FinFETs," (Invited Paper), Proc. of the NSTI Nanotech (WCM-Nanotech2012), Santa Clara, CA, Jun. 2012, vol. 2, pp. 784-787.

    8.  
  8. S. B. Chiah, X. Zhou, Z. H. Chen, H. M. Chen, and L. Yuan, "Unified Regional Approach to High Temperature SOI DC/AC Modeling," Proc. of the NSTI Nanotech (WCM-Nanotech2012), Santa Clara, CA, Jun. 2012, vol. 2, pp. 796-799.

    9.  
  9. J. B. Zhang and X. Zhou, "An Analytical 2DEG Model Considering the Two Lowest Subbands," Proc. of the NSTI Nanotech (WCM-Nanotech2012), Santa Clara, CA, Jun. 2012, vol. 2, pp. 734-737.

    10.  
  10. X. Zhou, "Physics-Based Compact Variability/Reliability Modeling for Emerging Double-Gate/Nanowire MOSFETs," (Invited Talk), 2011 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC2011), Tianjin, China, Nov. 17, 2011.

    11.  
  11. X. Zhou, S. H. Lin, and M. K. Srikanth, "Statistical Compact Modeling for Emerging Nanowire / FinFET Mismatch and Variance Studies," (Invited Paper), Proc. of the 6th International Conference on Materials for Advanced Technologies (ICMAT2011), Symposium W: Reliability and Variability of Emerging Devices for Future Technologies and ULSI Circuits and Systems, Singapore, June 2011, Paper W6-2.

    12.  
  12. X. Zhou, "Xsim: A Unified Compact Model for Bulk/SOI/DG/GAA MOSFETs," (Invited Paper), Proc. Nanotech (WCM-Nanotech2011), Boston, MA, Jun. 2011, vol. 2, pp. 726-731.

    13.  
  13. J. B. Zhang, X. Zhou, G. J. Zhu, and S. H. Lin, "Charge Partition in Lateral Nonuniformly-Doped Transistor," Proc. Nanotech (WCM-Nanotech2011), Boston, MA, Jun. 2011, vol. 2, pp. 784-787.

    14.  
  14. S. H. Lin, X. Zhou, Z. H. Chen, M. K. Srikanth, and J. B. Zhang, "Hot-Carrier-Induced Current Degradation in Deep Sub-Micron MOSFETs from Subthreshold to Strong Inversion Region," Proc. Nanotech (WCM-Nanotech2011), Boston, MA, Jun. 2011, vol. 2, pp. 806-809.

    15.  
  15. X. Zhou, G. Zhu, G. H. See, K. Chandrasekaran, S. B. Chiah, and K. Y. Lim, "Unification of MOS compact models with the unified regional modeling approach," (Invited Paper), Journal of Computational Electronics, Vol. 10, No. 1, pp. 121-135, 2011.

    16.  
  16. Z. H. Chen, X. Zhou, Y. Z. Hu, and M. K. Srikanth, "Neutral Interface Traps for Negative Bias Temperature Instability," Proc. of the 2011 IEEE Reliability Physics Symposium (IRPS2011), Monterey, CA, Apr. 2011, pp. 913-914.

    17.  
  17. X. Zhou, "Challenges and Trends in Unified Compact Modeling of Conventional (Bulk/SOI) and Emerging (Multigate/Nanowire) MOSFETs," (Keynote), International Symposium on Next-Generation Electronics (ISNE2010), Kaohsiung, Taiwan, November 2010, pp. 1-2.

    18.  
  18. X. Zhou, G. J. Zhu, M. K. Srikanth, S. H. Lin, Z. H. Chen, J. B. Zhang, and C. Q. Wei, "A Unified Compact Model for Emerging DG FinFETs and GAA Nanowire MOSFETs Including Long/Short-Channel and Thin/Thick-Body Effects," (Invited Paper), Proc. of the 10th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2010), Shanghai, China, Nov. 2010, pp. 1725-1728.

    19.  
  19. C. Q. Wei, Y.-Z. Xiong, X. Zhou, N. Singh, X.-J. Yuan, G. Q. Lo, L. Chan, and D.-L. Kwong, "Comparative Study of 1/f Noise Degradation Caused by Fowler–Nordheim Tunneling Stress in Silicon Nanowire Transistors and FinFETs," IEEE Trans. Electron Devices, Vol. 57, No. 10, pp. 2774-2779, October 2010.

    20.  
  20. C. Q. Wei, Y.-Z. Xiong, and X. Zhou, "Test Structure for Characterization of Low-Frequency Noise in CMOS Technologies," IEEE Trans. Instr. Meas., Vol. 57, No. 7, pp. 1860-1865, July 2010.

    21.  
  21. X. Zhou, G. J. Zhu, M. K. Srikanth, S. H. Lin, Z. H. Chen, J. B. Zhang, C. Q. Wei, Y. F. Yan, R. Selvakumar, and Z. H. Wang, "Xsim: Benchmark Tests for the Unified DG/GAA MOSFET Compact Model," Proc. of the NSTI Nanotech 2010 (WCM-Nanotech2010), Anaheim, CA, June 2010, Vol. 2, pp. 785-788.

    22.  
  22. G. J. Zhu, X. Zhou, Y. K. Chin, K. L. Pey, J. B. Zhang, G. H. See, S. H. Lin, Y. F. Yan, and Z. H. Chen, "Subcircuit Compact Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs," IEEE Trans. Electron Devices, Vol. 57, No. 4, pp. 772-781, April 2010.

    23.  
  23. Z. H. Chen, X. Zhou, G. J. Zhu, and S. H. Lin, "Interface-Trap Modeling for Silicon-Nanowire MOSFETs," Proc. of the 2010 IEEE Reliability Physics Symposium (IRPS2010), Anaheim, CA, May 2010, pp. 977-980.

    24.  
  24. X. Zhou, G. J. Zhu, S. H. Lin, Z. H. Chen, M. K. Srikanth, Y. F. Yan, R. Selvakumar, W. Chandra, J. B. Zhang, C. Q. Wei, Z. H. Wang, and P. Bathla, "Subcircuit Approach to Inventive Compact Modeling for CMOS Variability and Reliability," Proc. of the 12th International Symposium on Integrated Circuits, Devices & Systems (ISIC2009), Singapore, Dec. 2009, pp. 133-138.

    25.  
  25. X. Zhou, G. J. Zhu, S. H. Lin, C. Q. Wei, J. B. Zhang, Z. H. Chen, M. K. Srikanth, R. Selvakumar, and Y. F. Yan, "Unification of MOSFET Compact Models with the Unified Regional Modeling Approach," (Invited Talk), MOS-AK Workshop, Baltimore, MD, Dec. 9, 2009.

    26.  
  26. Z. H. Chen, X. Zhou, G. J. Zhu, and S. H. Lin, "Surface Recombination/Generation Velocity in Metal-Oxide-Silicon Field-Effect Transistors," Proc. of the 2009 IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC2009), Xi'an, China, Dec. 2009, paper 6.4.

    27.  
  27. Z. H. Chen, X. Zhou, and G. J. Zhu, "Effects of Translational Layer of Gate Insulator on Recombination DC Current-Voltage Lineshape in Metal-Oxide-Silicon Transistors," Jpn. J. Appl. Phys., Vol. 48, No. 9, 091403, 2009.

    28.  
  28. C. Q. Wei, Y. Jiang, Y.-Z. Xiong, X. Zhou, N. Singh, S. C. Rustagi, G. Q. Lo, and D.-L. Kwong, "Impact of Gate Electrode on 1/f Noise of Gate-All-Around Silicon Nanowire Transistors," IEEE Electron Device Lett., Vol. 30, No. 10, pp. 1081-1083, Oct. 2009.

    29.  
  29. G. J. Zhu, X. Zhou, Y. K. Chin, K. L. Pey, G. H. See, S. H. Lin, and J. B. Zhang, “Subcircuit Compact Model for Dopant-Segregated Schottky Silicon-Nanowire MOSFETs,” Proc. of the 2009 International Conference on Solid State Devices and Materials (SSDM2009), Sendai, Japan, Oct. 2009, pp. 402-403.

    30.  
  30. C. Q. Wei, Y.-Z. Xiong, X. Zhou, "Investigation of Low-Frequency Noise in N-Channel FinFETs From Weak to Strong Inversion," IEEE Trans. Electron Devices, Vol. 56, No. 11, pp. 2800-2810, November 2009.

    31.  
  31. C. Q. Wei, Y.-Z. Xiong, X. Zhou, N. Singh, S. C. Rustagi, G. Q. Lo, and D.-L. Kwong, "Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs in the Subthreshold Region," IEEE Electron Device Lett., Vol. 30, No. 6, pp. 668-671, June 2009.

    32.  
  32. X. Zhou, G. J. Zhu, G. H. See, J. B. Zhang, S. H. Lin, C. Q. Wei, Z. H. Chen, M. K. Srikanth, Y. F. Yan, R. Selvakumar, and W. Chandra, “Unified Compact Modeling for Bulk/SOI/FinFET/SiNW MOSFETs,” (Invited Paper), Proc. of the 2nd International Workshop on Electron Devices and Semiconductor Technology (IEDST2009), Mumbai, India, June 2009, Paper I8.

    33.  
  33. X. Zhou, G. J. Zhu, M. K. Srikanth, R. Selvakumar, Y. F. Yan, W. Chandra, J. B. Zhang, S. H. Lin, C. Q. Wei, and Z. H. Chen, "Compact Model Application to Statistical/Probabilistic Technology Variations," Proc. of the 12th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2009), Houston, TX, May 2009, Vol. 3, pp. 612-615.

    34.  
  34. G. J. Zhu, X. Zhou, G. H. See, S. H. Lin, C. Q. Wei, and J. B. Zhang, "A Unified Compact Model for FinFET and Silicon Nanowire MOSFETs," Proc. of the 12th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2009), Houston, TX, May 2009, Vol. 3, pp. 588-591.

    35.  
  35. S. H. Lin, X. Zhou, G. H. See, G. J. Zhu, C. Q. Wei, J. B. Zhang, and Z. H. Chen, "A Simple, Accurate Capacitance-Voltage Model of Undoped Silicon Nanowire MOSFETs," Proc. of the 12th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2009), Houston, TX, May 2009, Vol. 3, pp. 643-646.

    36.  
  36. C. Q. Wei, Y.-Z. Xiong, and X. Zhou, "1/f Noise Model for Double-Gate FinFET Biased in Weak Inversion," Proc. of the 12th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2009), Houston, TX, May 2009, Vol. 3, pp. 639-642.

    37.  
  37. Z. H. Chen, X. Zhou, G. H. See, Z. M. Zhu, and G. J. Zhu, "Interface Traps in Surface-Potential-Based MOSFET Models," Proc. of the 12th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2009), Houston, TX, May 2009, Vol. 3, pp. 542-545.

    38.  
  38. G. J. Zhu, X. Zhou, T. S. Lee, L. K. Ang, G. H. See, S. H. Lin, Y. K. Chin, and K. L. Pey, "A Compact Model for Undoped Silicon-Nanowire MOSFETs with Schottky-Barrier Source/Drain," IEEE Trans. Electron Devices, Vol. 56, No. 5, pp. 1100-1109, May 2009.

    39.  
  39. X. Zhou, G. H. See, G. J. Zhu, S. H. Lin, C. Q. Wei, nd J. B. Zhang, "Unified Regional Modeling Approach to Emerging Multiple-Gate/Nanowire MOSFETs," (Invited Paper), Proc. of the 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2008), Beijing, China, October 20-23, 2008, Paper B1.2.

    40.  
  40. G. J. Zhu, X. Zhou, T. S. Lee, L. K. Ang, G. H. See, and S. H. Lin, "A Compact Model for Undoped Symmetric Double-Gate MOSFETs with Schottky-Barrier Source/Drain," Proc. of the 2008 European Solid-State Device Research Conference (ESSDERC2008), Edinburgh, UK, September 15-19, 2008, pp. 182-185.

    41.  
  41. G. J. Zhu, G. H. See, S. H. Lin, C. Q. Wei, J. B. Zhang, Z. H. Chen, R. Selvakumar, and X. Zhou, "Xsim: Unification of MOSFET Compact Models with the Unified Regional Modeling Approach," poster presentation at the MOS-AK/ESSDERC/ESSCIRC Workshop, Edinburgh, UK, September 19, 2008.

    42.  
  42. G. J. Zhu, G. H. See, S. H. Lin, and X. Zhou, "“Ground-Referenced” Model for Three-Terminal Symmetric Double-Gate MOSFETs with Source/Drain Symmetry," IEEE Trans. Electron Devices, Vol. 55, No. 9, pp. 2526-2530, September 2008.

    43.  
  43. C. Q. Wei, G. H. See, X. Zhou, and L. Chan, "A New Impact-Ionization Current Model Applicable to Both Bulk and SOI MOSFETs by Considering Self-Lattice-Heating," IEEE Trans. Electron Devices, Vol. 55, No. 9, pp. 2378-2385, September 2008.

    44.  
  44. X. Zhou, G. H. See, G. J. Zhu, Z. M. Zhu, S. H. Lin, C. Q. Wei, A. Srinivas, and J. B. Zhang, "New Properties and New Challenges in MOS Compact Modeling," Proc. of the 11th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2008), Boston, MA, June 2-5, 2008, Vol. 3, pp. 750-755.

    45.  
  45. G. H. See, X. Zhou, G. Zhu, Z. Zhu, S. Lin, C. Wei, J. Zhang, and A. Srinivas, "Unified Regional Surface Potential for Modeling Common-Gate Symmetric/Asymmetric Double-Gate MOSFETs with Any Body Doping," Proc. of the 11th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2008), Boston, MA, June 2-5, 2008, Vol. 3, pp. 770-773.

    46.  
  46. G. H. See, X. Zhou, G. Zhu, Z. Zhu, S. Lin, C. Wei, J. Zhang, and A. Srinivas, "Unified Regional Surface Potential for Modeling Common-Gate Symmetric/Asymmetric Double-Gate MOSFETs with Quantum Mechanical Correction," Proc. of the 11th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2008), Boston, MA, June 2-5, 2008, Vol. 3, pp. 756-759.

    47.  
  47. G. J. Zhu, G. H. See, X. Zhou, Z. M. Zhu, S. H. Lin, C. Q. Wei, J. B. Zhang, and A. Srinivas, "Quasi-2D Surface-Potential Solution to Three-Terminal Undoped Symmetric Double-Gate Schottky-Barrier MOSFETs," Proc. of the 11th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2008), Boston, MA, June 2-5, 2008, Vol. 3, pp. 760-763.

    48.  
  48. C. Q. Wei, Y. Z. Xiong, X. Zhou, and L. Chan, "A Technique for Constructing RTS Noise Model Based on Statistical Analysis," to appear in Proc. of the 11th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2008), Boston, MA, June 2-5, 2008, Vol. 3, pp. 885-888.

    49.  
  49. X. Zhou, G. H. See, G. J. Zhu, Z. M. Zhu, S. H. Lin, C. Q. Wei, A. Srinivas, and J. B. Zhang, "New Challenges in MOS Compact Modeling for Future Generation CMOS," (Invited Paper), Proc. of the 2008 IEEE International Nanoelectronics Conference (INEC2008), Shanghai, China, March 24-28, 2008.

    50.  
  50. G. H. See, X. Zhou, K. Chandrasekaran, S. B. Chiah, Z. M. Zhu, C. Q. Wei, S. H. Lin, G. J. Zhu, and G. H. Lim, "A Compact Model Satisfying Gummel Symmetry in Higher Order Derivatives and Applicable to Asymmetric MOSFETs," IEEE Trans. Electron Devices, Vol. 55, No. 2, pp. 624-631, February 2008.

    51.  
  51. X. Zhou, Z. M. Zhu, S. C. Rustagi, G. H. See, G. J. Zhu, S. H. Lin, C. Q. Wei, and G. H. Lim, "Rigorous Surface-Potential Solution for Undoped Symmetric Double-Gate MOSFETs Considering Both Electrons and Holes at Quasi Nonequilibrium," IEEE Trans. Electron Devices, Vol. 55, No. 2, pp. 616-623, February 2008.

    52.  
  52. G. H. Lim, X. Zhou, K. Khu, Y. K. Yoo, F. Poh, G. H. See, Z. M. Zhu, C. Q. Wei, S. H. Lin, and G. J. Zhu, “Physics based scalable MOSFET mismatch model for statistical circuit simulation,” Proc. of the 2007 IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC2007), Tainan, December 2007, pp. 1063-1066.

    53.  
  53. G. H. Lim, X. Zhou, K. Khu, Y. K. Yoo, F. Poh, G. H. See, Z. M. Zhu, C. Q. Wei, S. H. Lin, and G. J. Zhu, “Impact of BEOL, multi-fingered layout design, and gate protection diode on intrinsic MOSFET threshold voltage mismatch,” Proc. of the 2007 IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC2007), Tainan, December 2007, pp. 1059-1062.

    54.  
  54. C. Q. Wei, X. Zhou, and G. H. See, “A New Electric-field-driven Impact Ionization Current Model Applicable to Both Bulk and SOI MOSFETs by Considering Self-lattice-heating,” the 2007 International Semiconductor Device Research Symposium (ISDRS2007), College Park, MD, December 2007.

    55.  
  55. Z. Zhu, X. Zhou, S. C. Rustagi, G. H. See, S. Lin, G. Zhu, C. Wei, and J. Zhang, "Analytic and explicit current model of undoped double-gate MOSFETs," Electron. Lett., Vol. 43, No. 25, pp. 1464-1466, December 2007.

    56.  
  56. S. H. Lin, X. Zhou, G. H. See1, Z. M. Zhu, G. H. Lim, C. Q. Wei, G. J. Zhu, Z. H., Yao, X. F. Wang, M. Yee, L. N. Zhao, Z. F. Hou, L. K. Ang, T. S. Lee, W. Chandra, "A Rigorous Surface-Potential-Based I-V Model for Undoped Cylindrical Nanowire MOSFETs," Proc. of the 7th International Conference on Nanotechnology (IEEE-Nano2007), Hong Kong, August 2-5, 2007, pp. 889-892.

    57.  
  57. X. Zhou, G. H. See, Z. M. Zhu, S. H. Lin, C. Q. Wei, G. J. Zhu, G. H. Lim, "Unified Compact Modeling of Emerging Multiple-Gate MOSFETs," (Invited Paper), Proc. of the 2007 International Workshop on Electron Devices and Semiconductor Technology (IEDST2007), Beijing, China, June 4, 2007, pp. 31-36.

    58.  
  58. X. Zhou, G. H. See, G. J. Zhu, K. Chandrasekaran, Z. M. Zhu, S. Rustagi, S. H. Lin, C. Q. Wei, and G. H. Lim, "Unified Compact Model for Generic Double-Gate MOSFETs," (Invited Paper), Proc. of the 10th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2007), Santa Clara, CA, May 20-24, 2007, Vol. 3, pp. 538-543.

    59.  
  59. G. H. See, X. Zhou, K. Chandrasekaran, S. B. Chiah, Z. Zhu, G. H. Lim, C. Q. Wei, S. H. Lin, and G. J. Zhu, "Gummel Symmetry with Higher-order Derivatives in MOSFET Compact Models," Proc. of the 10th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2007), Santa Clara, CA, May 20-24, 2007, Vol. 3, pp. 613-616.

    60.  
  60. Z. M. Zhu, X. Zhou, K. Chandrasekaran, S. C. Rustagi, and G. H. See, "Explicit compact surface-potential and drain-current models for generic asymmetric double-gate MOSFETs," Jpn. J. Appl. Phys., Vol. 46, No. 4B, pp. 2067-2072, April 2007.

    61.  
  61. W. Z. Shangguan, T. C. Au Yeung, Z. M. Zhu, and X. Zhou, "General analytical Poisson solution for undoped generic two-gated metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., Vol. 90, No. 1, 012110, January 2007.

    62.  
  62. W. Z. Shangguan, X. Zhou, K. Chandrasekaran, Z. M. Zhu, S. C. Rustagi, S. B. Chiah, and G. H. See, "Surface-potential Solution for Generic Undoped MOSFETs with Two Gates," IEEE Trans. Electron Devices, Vol. 54, No. 1, pp. 169-172, January 2007.

    63.  
  63. K. Chandrasekaran, X. Zhou, S. B. Chiah, G. H. See, and S. C. Rustagi, "Implicit Analytical Surface/Interface Potential Solutions for Modeling Strained-Si MOSFETs," IEEE Trans. Electron Devices, Vol. 53, No. 12, pp. 3110-3117, December 2006.

    64.  
  64. W. Z. Shangguan, M. Saeys, and X. Zhou, "Surface-potential solutions to the Pao-Sah voltage equation," Solid-State Electron., Vol. 50, No. 7-8, pp. 1320-1329, July-August 2006.

    65.  
  65. X. Zhou, K. Chandrasekaran, G. H. See, Z. M. Zhu, G. H. Lim, S. H. Lin, C. Q. Wei, S. B. Chiah, M. Cheng, S. Chu, L.-C. Hsia, and S. Rustagi, "Towards Unification of MOS Compact Models with the Unified Regional Approach," (Invited Paper), Proc. of the 8th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2006), Shanghai, China, Oct. 23-26, 2006, pp. 1193-1197.

    66.  
  66. Z. M. Zhu, X. Zhou, K. Chandrasekaran, G. H. See, and S. C. Rustagi, "A Continuous, Explicit Drain-Current Model for Asymmetric Undoped Double-Gate MOSFETs," Proc. of the 2006 International Conference on Solid State Devices and Materials (SSDM2006), Pacifico Yokohama, Japan, Sept. 12-15, 2006, pp. 1042-1043.

    67.  
  67. X. Zhou, K. Chandrasekaran, S. B. Chiah, W. Z. Shangguan, Z. M. Zhu, G. H. See, S. M. Pandey, G. H. Lim, S. Rustagi, M. Cheng, S. Chu, and L.-C. Hsia, "Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling," (Invited Paper), Proc. of the NSTI Nanotech 2006 (WCM-MSM2006), Boston, MA, May 7-11, 2006, Vol. 3, pp. 652-657. Download PDF View Slides

    68.  
  68. G. H. See, S. B. Chiah, X. Zhou, K. Chandrasekaran, W. Z. Shangguan, Z. M. Zhu, G. H. Lim, S. M. Pandey, M. Cheng, S. Chu, and L.-C. Hsia, "Scalable MOSFET Short-channel Charge Model in All Regions," Proc. of the NSTI Nanotech 2006 (WCM-MSM2006), Boston, MA, May 7-11, 2006, Vol. 3, pp. 749-752. Download PDF View Slides 

    69.  
  69. K. Chandrasekaran, Z. M. Zhu, X. Zhou, W. Z. Shangguan, G. H. See, S. B. Chiah, S. C. Rustagi, and N. Singh, "Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach," Proc. of the NSTI Nanotech 2006 (WCM-MSM2006), Boston, MA, May 7-11, 2006, Vol. 3, pp. 792-795. Download PDF View Slides 

    70.  
  70. K. Chandrasekaran, X. Zhou, S. B. Chiah, W. Z. Shangguan, and G. H. See, L. K. Bera, N. Balasubramanian, and S. C. Rustagi, "Effect of Substrate Doping on the Capacitance–Voltage Characteristics of Strained-silicon pMOSFETs," IEEE Electron Device Lett., Vol. 27, No. 1, pp. 62-64, January 2006. Download PDF

    71.  
  71. K. Chandrasekaran, X. Zhou, S. B. Chiah, W. Z. Shangguan, G. H. See, L. K. Bera, N. Balasubramanian, S. C. Rustagi, "Extraction of physical parameters of strained-silicon MOSFETs from C-V measurement," Proc. of the 2005 European Solid-State Device Research Conference (ESSDERC2005), Grenoble, France, September 12-16, 2005, pp. 521-524. Download PDF View Slides

    72.  
  72. K. Chandrasekaran, S. B. Chiah, X. Zhou, W. Z. Shangguan, and G. H. See, "Physics-based Single-piece Charge Model for Strained-Si MOSFETs," IEEE Trans. Electron Devices, Vol. 52, No. 7, pp. 1555-1562, July 2005. Download PDF

    73.  
  73. W. Z. Shangguan, X. Zhou, S. B. Chiah, G. H. See, K. Chandrasekaran, "A Transfer-matrix Based Compact Gate Tunneling Current Model," the 3rd International Conference on Materials for Advanced Technologies (ICMAT-2005), Symposium L: Materials Physics at Interfaces, Singapore, July 3-8, 2005, Paper L-8-OR21.

    74.  
  74. X. Zhou, S. B. Chiah, K. Chandrasekaran, G. H. See, W. Z. Shangguan, S. M. Pandey, C. H. Ang, M. Cheng, and S. Chu, L.-C. Hsia, "Unified Regional Charge Model with Non-pinned Surface Potential," (Invited Paper), 2nd International Workshop on Compact Modeling (IWCM-2005) at the Asia and South Pacific Design Automation Conference (ASP-DAC2005), Shanghai, January 20, 2005.

    75.  
  75. X. Zhou, S. B. Chiah, K. Chandrasekaran, G. H. See, W. Z. Shangguan, S. M. Pandey, M. Cheng, S. Chu, L.-C. Hsia, "A Compact Model for Future Generation Predictive Technology Modeling and Circuit Simulation," (Invited Paper), Proc. of the 12th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2005), Kraków, Poland, June 22-25, 2005, pp. 881-886. Download PDF View Slides

    76.  
  76. W. Z. Shangguan, X. Zhou, S. B. Chiah, G. H. See, and K. Chandrasekaran, "Compact gate-current model based on transfer-matrix method," J. Appl. Phys., Vol. 97, 123709, 15 June 2005. Download PDF

    77.  
  77. S. B. Chiah, X. Zhou, K. Chandrasekaran, W. Z. Shangguan, G. H. See, and S. M. Pandey, "Single-piece polycrystalline silicon accumulation/depletion/inversion model with implicit/explicit surface-potential solutions," Appl. Phys. Lett., Vol. 86, No. 20, 202111, May 2005. Download PDF

    78.  
  78. X. Zhou, S. B. Chiah, K. Chandrasekaran, G. H. See, W. Shangguan, S. M. Pandey, M. Cheng, S. Chu, and L.-C. Hsia, "Unified Regional Charge-based Versus Surface-potential-based Compact Modeling Approaches," (Invited Paper), Proc. of the NSTI Nanotech 2005 (WCM-MSM2005), Anaheim, CA, May 8-12, 2005, Vol. WCM, pp. 25-30. Download PDF View Slides

    79.  
  79. S. B. Chiah, X. Zhou, K. Chandrasekaran, G. H. See, W. Shangguan, S. M. Pandey, M. Cheng, S. Chu, and L.-C. Hsia, "One-iteration Parameter Extraction for Length/width-dependent Threshold Voltage and Unified Drain Current Model," Proc. of the NSTI Nanotech 2005 (WCM-MSM2005), Anaheim, CA, May 8-12, 2005, Vol. WCM, pp. 143-146. Download PDF View Slides 

    80.  
  80. G. H. See, S. B. Chiah, X. Zhou, K. Chandrasekaran, W. Shangguan, S. M. Pandey, M. Cheng, S. Chu, and L.-C. Hsia, "Unified Regional Charge-based MOSFET Model Calibration," Proc. of the NSTI Nanotech 2005 (WCM-MSM2005), Anaheim, CA, May 8-12, 2005, Vol. WCM, pp. 174-150. Download PDF View Slides 

    81.  
  81. X. Zhou, S. B. Chiah, K. Chandrasekaran, G. H. See, W. Shangguan, S. M. Pandey, C. H. Ang, M. Cheng, S. Chu, and L.-C. Hsia, "Unified Regional Charge Model with Non-pinned Surface Potential," (Invited Paper), Proc. of the 2nd International Workshop on Compact Modeling (IWCM-2005), pp. 13-17, presented at the Asia and South Pacific Design Automation Conference (ASP-DAC2005), Shanghai, January 18-21, 2005. Download PDF View Slides

    82.  
  82. X. Zhou, S. B. Chiah, K. Chandrasekaran, W. Shangguan, G. H. See, C. H. Ang, S. Chu, and L.-C. Hsia, "Xsim: Unified Regional Approach to Compact Modeling for Next Generation CMOS," (Invited Paper), Proc. of the 7th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT-2004), Beijing, October 18-21, 2004, pp. 924-929. Download PDF View Slides

    83.  
  83. X. Zhou, S. B. Chiah, and K. Y. Lim, "A compact deep-submicron MOSFET gds model including hot-electron and thermoelectric effects," Solid-State Electron., Vol. 48, No. 12, pp. 2125-2131, December 2004. Download PDF

    84.  
  84. S. B. Chiah, X. Zhou, K. Y. Lim, L. Chan, and S. Chu, "Source-Drain Symmetry in Unified Regional MOSFET Model," IEEE Electron Device Lett., Vol. 25, No. 5, pp. 311-313, May 2004. Download PDF

    85.  
  85. X. Zhou, S. B. Chiah, K. Chandrasekaran, K. Y. Lim, L. Chan, and S. Chu, "Unified Regional Approach to Consistent and Symmetric DC/AC Modeling of Deep-Submicron MOSFETs," (Invited Paper), Proc. of the 7th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2004), Boston, MA, March 7-11, 2004, Vol. 2. Download PDF View Slides

    86.  
  86. S. B. Chiah, X. Zhou, K. Chandrasekaran, K. Y. Lim, L. Chan, and S. Chu, "Threshold-Voltage-Based Regional Modeling of MOSFETs with Symmetry and Continuity," Proc. of the 7th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2004), Boston, MA, March 7-11, 2004, Vol. 2, pp. 175-178. Download PDF View Slides

    87.  
  87. K. Chandrasekaran, X. Zhou, and S. B. Chiah, "Physics-Based Scalable Threshold-Voltage Model for Strained-Silicon MOSFETs," Proc. of the 7th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2004), Boston, MA, March 7-11, 2004, Vol. 2, pp. 179-182. Download PDF View Slides

    88.  
  88. X. Zhou, "The Missing Link to Seamless Simulation," (Invited Feature Article), IEEE Circuits Devices Mag., Vol. 19, No. 3, pp. 9-17, May 2003. Download PDF

    89.  
  89. X. Zhou, S. B. Chiah, and K. Y. Lim, "A Technology-Based Compact Model for Predictive Deep-Submicron MOSFET Modeling and Characterization," (Invited Paper), Proc. of the 6th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2003), San Francisco, CA, February 23-27, 2003, Vol. 2, pp. 266-269. Download PDF View Slides

    90.  
  90. S. B. Chiah, X. Zhou, and K. Y. Lim, "Unified Length-/Width-Dependent Threshold Voltage Model with Reverse Short-Channel and Inverse Narrow-Width Effects," Proc. of the 6th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2003), San Francisco, CA, February 23-27, 2003, Vol. 2, pp. 338-341. Download PDF View Slides

    91.  
  91. S. B. Chiah, X. Zhou, and K. Y. Lim, "Unified Length-/Width-Dependent Drain Current Model for Deep-Submicron MOSFETs," Proc. of the 6th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2003), San Francisco, CA, February 23-27, 2003, Vol. 2, pp. 342-345. Download PDF View Slides

    92.  
  92. K. Y. Lim and X. Zhou, "An analytical effective channel-length modulation model for velocity overshoot in submicron MOSFETs based on energy-balance formulation," Microelectronics Reliability, Vol. 42, No. 12, pp. 1857-1864, December 2002. Download PDF

    93.  
  93. X. Zhou, "Multi-Level Modeling of Deep-Submicron MOSFETs and ULSI Circuits," (Invited Paper), Proc. of the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002), Wroclaw, Poland, June 20-22, 2002, pp. 39-44. Download PDF View Slides

    94.  
  94. X. Zhou and K. Y. Lim, "De-embedding Length-Dependent Edge-Leakage Current in Shallow Trench Isolation Submicron MOSFETs," Solid-State Electron., Vol. 46, No. 5, pp. 769-772, May 2002. Download PDF

    95.  
  95. X. Zhou, "Xsim: A Compact Model for Bridging Technology Developers and Circuit Designers," (Invited Paper), Proc. of  the 5th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2002), San Juan, Puerto Rico, April 22-25, 2002, Vol. 1, pp. 710-714. Download PDF View Slides

    96.  
  96. S. B. Chiah, X. Zhou, K. Y. Lim, A. See, and L. Chan, "Physically-Based Approach to Deep-Submicron MOSFET Compact Model Parameter Extraction," Proc. of the 5th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2002), San Juan, Puerto Rico, April 22-25, 2002, Vol. 1, pp. 750-753. Download PDF View Slides

    97.  
  97. K. Y. Lim and X. Zhou, "Compact Model for Manufacturing Design and Fluctuation Study," Proc. of the 5th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2002), San Juan, Puerto Rico, April 22-25, 2002, Vol. 1, pp. 746-749. Download PDF View Slides

    98.  
  98. K. Y. Lim and X. Zhou, "MOSFET Subthreshold Compact Modeling with Effective Gate Overdrive," IEEE Trans. Electron Devices, Vol. 49, No. 1, pp. 196-199, January 2002. Download PDF

    99.  
  99. X. Zhou and S. B. Chiah, "XSIM/DOUST: A Compact Model for Design and Optimization of Ultra-Small Transistors," EEE Research Bulletin, School of Electrical and Electronic Engineering, Nanyang Technological University, January 2002, pp. 12-13. Download PDF

    100.  
  100. K. Y. Lim, X. Zhou, and Y. Wang, "Physics-Based Threshold Voltage Modeling with Reverse Short Channel Effect," J. Modeling Simulation Microsystems (JMSM), Vol. 2, No. 1, pp. 51-55, 2001. Download PDF

    101.  
  101. X. Zhou, S. B. Chiah, and K. Y. Lim, "A Compact Deep-Submicron MOSFET gds Model Including Hot-Electron and Thermoelectric Effects," Proc. of the 2001 International Semiconductor Device Research Symposium (ISDRS-01), Washington DC, December 5-7, 2001, pp. 653-656. Download PDF

    102.  
  102. X. Zhou, S. B. Chiah, K. Y. Lim, Y. Wang, X. Yu, S. Chwa, A. See, and L. Chan, "Technology-Dependent Modeling of Deep-Submicron MOSFET's and ULSI Circuits," (Invited Paper), Proc. of the 6th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT-2001), Shanghai, October 22-25, 2001, Vol. 2, pp. 855-860. Download PDF View Slides

    103.  
  103. Y. Wang, X. Zhou, K. Y. Lim, and S. B. Chiah, "Investigation of MOSFET Series Resistance by Numerical Simulation and Compact Modeling," Proc. of the 9th International Symposium on Integrated Circuits, Devices & Systems (ISIC2001), Singapore, September 3-5, 2001, pp. 238-241. Download PDF

    104.  
  104. X. Zhou and K. Y. Lim, "Unified MOSFET Compact I-V Model Formulation through Physics-Based Effective Transformation," IEEE Trans. Electron Devices, Vol. 48, No. 5, pp. 887-896, May 2001. Download PDF

    105.  
  105. X. Zhou, K. Y. Lim, and W. Qian, "Threshold Voltage Definition and Extraction for Deep-Submicron MOSFETs," Solid-State Electron., Vol. 45, No. 3, pp. 507-510, April 2001. Download PDF

    106.  
  106. X. Zhou and K. Y. Lim, "Experimental Determination of Electrical, Metallurgical, and Physical Gate Lengths of Submicron MOSFET's," Proc. of the 4th International Conference on Modeling and Simulation of Microsystems (MSM2001), Hilton Head Island, SC, March 19-21, 2001, pp. 44-47. Download PDF Browse with IE

    107.  
  107. S. B. Chiah, X. Zhou, K. Y. Lim, Y. Wang, A. See, and L. Chan, "Semi-Empirical Approach to Modeling Reverse Short-Channel Effect in Submicron MOSFET's," Proc. of the 4th International Conference on Modeling and Simulation of Microsystems (MSM2001), Hilton Head Island, SC, March 19-21, 2001, pp. 486-489. Download PDF View Slides

    108.  
  108. K. Y. Lim and X. Zhou, "A Physically-Based Semi-Empirical Effective Mobility Model for MOSFET Compact I-V Modeling," Solid-State Electron., Vol. 45, No. 1, pp. 193-197, January 2001. Download PDF

    109.  
  109. W. Qian, X. Zhou, Y. Wang, and K. Y. Lim, "Surface-Potential-Based Model of Reverse Short Channel Effect in Submicrometer MOSFETs with Nonuniform Lateral Channel Doping," in Design, Modeling, and Simulation in Microelectronics, Bernard Courtois, Serge N. Demidenko, L. Y. Lau, Editors, Proc. of SPIE, Vol. 4228, pp. 243-248, 2000.  Presented at the 2nd International Symposium on Microelectronics and Assembly (ISMA2000), Singapore, November 27 - December 1, 2000. Download PDF Browse with IE

    110.  
  110. Y. Wang, K. Y. Lim, W. Qian, and X. Zhou, "Investigation of Reverse Short Channel Effect with Numerical and Compact Models," in Design, Modeling, and Simulation in Microelectronics, Bernard Courtois, Serge N. Demidenko, L. Y. Lau, Editors, Proc. of SPIE, Vol. 4228, pp. 366-373, 2000.  Presented at the 2nd International Symposium on Microelectronics and Assembly (ISMA2000), Singapore, November 27 - December 1, 2000. Download PDF Browse with IE

    111.  
  111. K. Y. Lim and X. Zhou, "A Physically-Based Semi-Empirical Series Resistance Model for Deep-Submicron MOSFET I-V Modeling," IEEE Trans. Electron Devices, Vol. 47, No. 6, June, pp. 1300-1302. Download PDF

    112.  
  112. X. Zhou and K. Y. Lim, "A Novel Approach to Compact I-V Modeling for Deep-Submicron MOSFET's Technology Development with Process Correlation," Proc. of the 3rd International Conference on Modeling and Simulation of Microsystems (MSM2000), San Diego, CA, March 27-29, 2000, pp. 333-336. Download PDF View Slides

    113.  
  113. K. Y. Lim, X. Zhou, and Y. Wang, "Modeling of Threshold Voltage with Reverse Short Channel Effect," Proc. of the 3rd International Conference on Modeling and Simulation of Microsystems (MSM2000), San Diego, CA, March 27-29, 2000, pp. 317-320. Download PDF View Slides

    114.  
  114. W. Qian, X. Zhou, Y. Wang, and K. Y. Lim, "A Velocity-Overshoot Subthreshold Current Model for Deep-Submicrometer MOSFET Devices," Proc. of the 3rd International Conference on Modeling and Simulation of Microsystems (MSM2000), San Diego, CA, March 27-29, 2000, pp. 396-399. Download PDF

    115.  
  115. X. Zhou, K. Y. Lim, and D. Lim, "A General Approach to Compact Threshold Voltage Formulation Based on 2-D Numerical Simulation and Experimental Correlation for Deep-Submicron ULSI Technology Development," IEEE Trans. Electron Devices, Vol. 47, No. 1, pp. 214-221, January 2000. Download PDF

    116.  
  116. X. Zhou and K. Y. Lim, "A Compact MOSFET Ids Model for Channel-Length Modulation Including Velocity Overshoot," Proc. of the 1999 International Semiconductor Device Research Symposium (ISDRS-99), Charlottesville, VA, December 1-3, 1999, pp. 423-426. Download PDF View Slides

    117.  
  117. X. Zhou, K. Y. Lim, and D. Lim, "A New 'Critical-Current at Linear-Threshold' Method for Direct Extraction of Deep-Submicron MOSFET Effective Channel Length," IEEE Trans. Electron Devices, Vol. 46, No. 7, pp. 1492-1494, July 1999. Download PDF

    118.  
  118. X. Zhou, K. Y. Lim, and D. Lim, "A Predictive Length-Dependent Saturation Current Model Based on Accurate Threshold Voltage Modeling," Proc. of the 2nd Modeling and Simulation of Microsystems (MSM99), San Juan, Puerto Rico, U.S.A., April 19-21, 1999, pp. 423-426. Download PDF View Slides

    119.  
  119. X. Zhou, K. Y. Lim, and D. Lim, "A Simple and Unambiguous Definition of Threshold Voltage and Its Implications in Deep-Submicron MOS Device Modeling," IEEE Trans. Electron Devices, Vol. 46, No. 4, pp. 807-809, April 1999. Download PDF

    120.  
  120. K. Y. Lim and X. Zhou, "Modelling of Threshold Voltage with Non-uniform Substrate Doping," Proc. of the 1998 IEEE International Conference on Semiconductor Electronics (ICSE’98), Malaysia, November 24-26, 1998, pp. 27-31. Download PDF

    121.  
  121. K. Y. Lim, X. Zhou, D. Lim, Y. Zu, H. M. Ho, K. Loiko, C. K. Lau, M. S. Tse, and S. C. Choo, "A Predictive Semi-Analytical Threshold Voltage Model for Deep-Submicron MOSFET's," Proc. of the IEEE Hong Kong Electron Devices Meeting (HKEDM98), Hong Kong, August 29, 1998, pp. 114-117. Download PDF

    122.  
  122. X. Zhou, "Process-Dependent MOS Threshold Voltage Formulation Based on 2-D Process and Device Simulations," Proc. of  the 7th International Symposium on IC Technology, Systems & Applications (ISIC-97), Singapore, September 10-12, 1997, pp. 235-238. Download PDF

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  63. "Unified Compact Modeling of Emerging Multiple-Gate MOSFETs," Invited Talk (IEEE EDS Distinguished Lecture Mini-colloquium), 13th Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT-HK/Singapore), Singapore, July 25, 2007.

    64.  
  64. "Unified Compact Modeling of Emerging Multiple-Gate MOSFETs," Invited Talk (IEEE EDS Distinguished Lecture Mini-colloquium), 13th Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT-HK/Singapore), Hong Kong, July 23, 2007.

    65.  
  65. "Unified Compact Modeling of Emerging Multiple-Gate MOSFETs," (Invited Paper), the 2007 International Workshop on Electron Devices and Semiconductor Technology (IEDST2007), Beijing, China, June 4, 2007.

    66.  
  66. "Unified Compact Model for Generic Double-Gate MOSFETs," (Invited Paper), Workshop on Compact Modeling, NSTI Nanotech 2007 (WCM-Nanotech2007), Santa Clara, CA, May 22, 2007.

    67.  
  67. "Compact Modeling: Computational Investigation of Novel Device Structures and Concepts using TCAD," Invited Short Course, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Malaysia, May 18, 2007.

    68.  
  68. "Compact Modeling: Parameter Extraction and Circuit Simulation," Invited Short Course, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Malaysia, May 17, 2007.

    69.  
  69. "Compact Modeling: Formulation and Characterization," Invited Short Course, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Malaysia, May 16, 2007.

    70.  
  70. "Compact Modeling: Overview, Introduction and Basic Concepts," Invited Short Course, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Malaysia, May 15, 2007.

    71.  
  71. "Towards Unification of MOS Compact Models with the Unified Regional Approach," (Invited Paper), the 8th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2006), Shanghai, China, Oct. 24, 2006.

    72.  
  72. "Unified Regional Approach to MOS Transistor Compact Modeling for Circuit Simulation," Invited Talk, Altera Corp., San Jose, CA, August 11, 2006.

    73.  
  73. "Towards Unification of MOSFET Compact Models with the Unified Regional Approach," Invited Talk, Advanced Micro Devices, Sunnyvale, CA, August 11, 2006.

    74.  
  74. "Towards Unification of MOSFET Compact Models with the Unified Regional Approach," Invited Talk, Cadence Design Systems, San Jose, CA, August 9, 2006.

    75.  
  75. "Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling," (Invited Paper), Workshop on Compact Modeling, NSTI Nanotech 2006 (WCM-MSM2006), Boston, MA, May 9, 2006.

    76.  
  76. "Extraction of physical parameters of strained-silicon MOSFETs from C-V measurement," the 2005 European Solid-State Device Research Conference (ESSDERC2005), Grenoble, France, September 15, 2005.

    77.  
  77. "A Compact Model for Future Generation Predictive Technology Modeling and Circuit Simulation," (Invited Paper), the 12th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2005), Kraków, Poland, June 23, 2005.

    78.  
  78. "Unified Regional Charge-based Versus Surface-potential-based Compact Modeling Approaches," (Invited Paper), Workshop on Compact Modeling, NSTI Nanotech 2005 (WCM-MSM2005), Anaheim, CA, May 10, 2005.

    79.  
  79. "Scalable Technology in the Nanoelectronics Era: Top-down versus Bottom-up," 1st NTU Nanotech Symposium, Nanyang Technological University, Singapore, January 29, 2005.

    80.  
  80. "The Missing Link to Seamless Simulation," Invited Talk (IEEE EDS Distinguished Lecture Program), Fudan University, Shanghai, January 20, 2005.

    81.  
  81. "Unified Regional Charge Model with Non-pinned Surface Potential," (Invited Paper), the 2nd International Workshop on Compact Modeling (IWCM-2005), Shanghai, January 20, 2005.

    82.  
  82. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," Invited Talk, Advanced Micro Devices, Sunnyvale, CA, December 18, 2004.

    83.  
  83. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," Invited Talk, Silicon Storage Technology, Sunnyvale, CA, December 10, 2004.

    84.  
  84. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," Invited Talk (IEEE EDS Distinguished Lecturer Program), CEC Huada Electronic Design Co., Ltd., Beijing, September 22, 2004.

    85.  
  85. "Xsim: Unified Regional Approach to Compact Modeling for Next Generation CMOS," (Invited Paper), the 7th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT-2004), Beijing, October 19, 2004.

    86.  
  86. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," Invited Talk (IEEE EDS Distinguished Lecture Mini-colloquium), 5th Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT-HK), Hong Kong, September 18, 2004.

    87.  
  87. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," Invited Talk (IEEE EDS Distinguished Lecture Mini-colloquium), 4th Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT04), Singapore, July 12, 2004.

    88.  
  88. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," SRC Annual Review Presentation, Durham, NC, USA, June 29, 2004.

    89.  
  89. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," Faculty Presentation - SRC Project Review, Chartered Semiconductor Manufacturing, Singapore, April 27, 2004.

    90.  
  90. "Scalable RF CMOS with Unified Regional Compact Model and Subcircuit Expansion Approach," Workshop on Nanoscale CMOS for High Frequency Applications, Institute of Microelectronics, Singapore, April 26, 2004.

    91.  
  91. "Unified Regional Approach to Consistent and Symmetric DC/AC Modeling of Deep-Submicron MOSFETs," (Invited Paper), Workshop on Compact Modeling, the 7th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2004), Boston, MA, March 9, 2004.

    92.  
  92. "Unified Regional Approach to Consistent and Symmetric DC/AC Modeling of Deep-Submicron MOSFETs," CNEG lunch-time seminar series, Nanyang Technological University, February 28, 2004.

    93.  
  93. "The Missing Link to Seamless Simulation," Invited Talk (IEEE EDS Distinguished Lecture Mini-colloquium), 3rd Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT-Singapore), Singapore, October 15, 2003.

    94.  
  94. "A Technology-Based Compact Model for Predictive Deep-Submicron MOSFET Modeling and Characterization," (Invited Paper), Workshop on Compact Modeling, the 6th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2003), San Francisco, CA, February 25, 2003.

    95.  
  95. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk (COE Visiting Professor), Research Center for Nanodevices and Systems, Hiroshima University, Japan, January 21, 2003.

    96.  
  96. "Multi-Level Modeling of Deep-Submicron CMOS ULSI Systems," Invited Talk (IEEE EDS Distinguished Lecturer Program), Microelectronics R&D Center, Chinese Academy of Sciences, Beijing, December 13, 2002; Institute of Microelectronics, Tsinghua University, Beijing, December 13, 2002.

    97.  
  97. "Multi-Level Modeling of Deep-Submicron MOSFETs and ULSI Circuits," (Invited Paper), the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002), Wroclaw, June 20, 2002.

    98.  
  98. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk, Swiss Federal Institute of Technology - Lausanne (EPFL), Lausanne, Switzerland, June 17, 2002.

    99.  
  99. "Xsim: A Compact Model for Bridging Technology Developers and Circuit Designers," (Invited Paper), Workshop on Compact Modeling, the 5th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2002), San Juan, Puerto Rico, April 24, 2002.

    100.  
  100. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk, Advanced Micro Devices, Inc., Sunnyvale, CA, April 16, 2002; Intel Corp., Santa Clara, CA, April 17, 2002; LSI Logic Corp., Santa Clara, CA, April 18, 2002.

    101.  
  101. "Technology-Dependent Modeling of Deep-Submicron MOSFET's and ULSI Circuits," (Invited Paper), the 6th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT-2001), Shanghai, October 23, 2001.

    102.  
  102. "MOSFET CompactI-V Modeling for Deep-Submicron Technology Development," Invited Talk (IEEE EDS Distinguished Lecturer Program), Fudan University, Shanghai, October 18, 2001; Wuxi Microelectronics R&D Center, Wuxi, October 24, 2001.

    103.  
  103. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk, Center for Integrated Systems, Stanford University, March 2, 2001; Electrical Engineering Department, University of California at Berkeley, March 22, 2001; LSI Logic Corp., Santa Clara, CA, March 26, 2001.

    104.  
  104. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk (IEEE EDS Distinguished Lecturer Program), Indian Institute of Technology, Bombay, December 9, 2000.

    105.  
  105. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development,"Invited Talk (IEEE EDS Distinguished Lecturer Program), Institute of Microelectronics, Tsinghua University, Beijing, September 6, 2000.

    106.  
  106. "A Novel Approach to Compact I-V Modeling for Deep-Submicron MOSFET's Technology Development with Process Correlation," the 3rd International Conference on Modeling and Simulation of Microsystems (MSM2000), San Diego, CA, March 29, 2000.

    107.  
  107. "Unified MOSFET Compact Model Formulation for Deep-Submicron Technology Development and Multi-Level Circuit Simulation," Invited Talk, Maxim Integrated Products, Inc., Sunnyvale, CA, March 23, 2000; LSI Logic Corp., Santa Clara, CA, March 24, 2000.

    108.  
  108. "Unified MOSFET Compact Model Formulation Through Physics-Based Effective Transformation for Multi-Level Technology Modeling and Circuit Design," Research Seminar, McMaster University, Canada, December 13, 1999; LSI Logic Corp., Fairport, NY, December 16, 1999; Eastman Kodak Co., Rochester, NY, December 17, 1999; Department of Electrical and Computer Engineering, University of Rochester, NY, December 17, 1999.

    109.  
  109. "A Compact MOSFET Ids Model for Channel-Length Modulation Including Velocity Overshoot," the 1999 International Semiconductor Device Research Symposium (ISDRS-99), Charlottesville, VA, December 2, 1999.

    110.  
  110. "MOSFET CompactI-V Modeling for Deep-Submicron Technology Development," E3 Seminar Series in Microelectronics (µE28) - Focus Workshop on Advanced Semiconductor Technology, Nanyang Technological University, September 13, 1999.

    111.  
  111. "A Novel Approach to Compact I-V Modeling for Deep-Submicron MOSFET's Technology Development," Invited Talk, Intel Corp., Santa Clara, CA, April 23, 1999.

    112.  
  112. "A Predictive Length-Dependent Saturation Current Model Based on Accurate Threshold Voltage Modeling," the 2nd International Conference on Modeling and Simulation of Microsystems (MSM99), San Juan, Puerto Rico, U.S.A., April 21, 1999.

    113.  
  113. "Compact Threshold Voltage Modeling for Deep-Submicron MOSFET's Based on Numerical Simulation, Empirical Formulation, and Experimental Correlation," Invited Talk, Advanced Micro Devices, Inc., Sunnyvale, CA, June 11, 1998; Avant! Corp., Fremont, CA, June 12, 1998; Motorola, Inc., Austin, TX, June 15, 1998; Texas Instruments, Inc., Dallas, TX, June 18, 1998.

    114.  
  114. "The Virtual Wafer Fab Technology for the Deep-Submicron ULSI Era," Microelectronics Division Seminar, Nanyang Technological University, February 11, 1998.

    115.  
  115. "Multi-Level TCAD Synthesis Approach to the Design and Optimization of Ultra-Small Transistors," Visiting Researcher Seminar, Advanced Micro Devices, Inc., Sunnyvale, CA, December 15, 1997.

    116.  
  116. "A Dynamic Timing Delay for Accurate Gate-Level Circuit Simulation," the 39th Midwest Symposium on Circuits and Systems (MWSCAS-96), Ames, Iowa, August 19, 1996.

Related Courses

  1. "Unified Compact Model for FinFETs and Nanowire MOSFETs," the 10th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2010), Tutorial, Shanghai, China, Nov. 1, 2010.

    2.  
  2. "Introduction to MOS Transistor Compact Modeling for Technology Development, Device Design, and Circuit Simulation," 5-day in-house training course, Altera Corp. (M) Sdn. Bhd., Malaysia, August 23-27, 2010.

    3.  
  3. "Introduction to MOS Transistor Compact Modeling for SPICE Circuit Simulation," in-house short course, Systems on Silicon Manufactoring Co. Pte. Ltd. (SSMC), Singapore, June 22, 2007.

    4.  
  4. "Introduction to MOS Transistor Compact Modeling for SPICE Circuit Simulation," in-house short course, United Microelectronics Corporation (UMCi), Singapore, June 22, 2006.

    5.  
  5. "Introduction to MOS Transistor Compact Modeling for SPICE Circuit Simulation," in-house short course, United Microelectronics Corporation (UMCi), Singapore, November 11, 2005.

    6.  
  6. "Introduction to MOS Transistor Compact Modeling for SPICE Circuit Simulation," in-house short course, Systems on Silicon Manufactoring Co. Pte. Ltd. (SSMC), Singapore, November 7, 2005.

    7.  
  7. "Multi-Level Modeling of Deep-Submicron CMOS ULSI Systems," 1-Day Short Course, organized by Center for Continuing Education, Nanyang Technological University, September 2, 2002. (Course Brochure)

    8.  
  8. "Mixed Analog–Digital Circuit Simulation: An Implicit Mixed-Mode Solution,"Technical Excellence Committee Seminar (1-day in-house course), Thomson Multimedia Pte. Ltd., Singapore, Apr. 19, 1996.

    9.  
  9. "Introduction to Process and Device Simulations with TSUPREM-4 and MEDICI," 3-Day In-House Workshop, TECH Semiconductor (Singapore) Pte. Ltd., Singapore, March 11-13, 1996.

    10.  
  10. "Introduction to Process and Device Simulations with TSUPREM-4 and MEDICI," 3-Day Public Workshop, jointly organized by National Supercomputing Resource Center and Novotronics Pte. Ltd., National Supercomputing Research Center, Singapore, February 5-7 and 12-14, 1996.

Related Theses

  1. Ning Ge, "Compact Modeling of EPROM Devices," Ph.D. Thesis, Nanyang Technological University (starting January 24, 2011)

    2.  
  2. Zhihuan Wang, "Numerical Characterization of Nanowire Transistors and Logic Gates with Parametric Variations for Probabilistic-CMOS," M.Sc. Dissertation.  (starting August 2009, finished January  2011).

    3.  
  3. Machavolu Kamakshi Srikanth, "Variability Study of Nanowire: A Compact Model Application," M.Sc. Dissertation.  (starting August 2008, finished July 2009).

    4.  
  4. Y. Zhang, "Numerical Studies of Schottky-Barrier MOSFETs," FYP A6185-081, Nanyang Technological University, 2008/09.

    5.  
  5. J. X. Chen, "Performance Comparisons of Ultra-Thin-Body SOI and Double-Gate MOSFETs," FYP A6187-081, Nanyang Technological University, 2008/09.

    6.  
  6. Y. Yu, "Numerical Studies of Schottky-Barrier MOSFETs," FYP A6188-081, Nanyang Technological University, 2008/09.

    7.  
  7. Z. X. Qiu, "Numerical Exploration of Asymmetrical MOSFETs," FYP A6176S, Nanyang Technological University, 2007/08.

    8.  
  8. L. G. Yu, "Numerical Studies of Silicon Nanowire GAA MOSFETs," FYP A6175S, Nanyang Technological University, 2007/08.

    9.  
  9. J. B. Zhang, "Compact Modeling of Non-classical MOSFETs," Ph.D. Thesis, Nanyang Technological University (starting 8/2007, in progress)

    10.  
  10. G. J. Zhu, "Compact Modeling of Ultra-Thin Body Silicon-on-Insulator MOSFETs," Ph.D. Thesis, Nanyang Technological University (starting 1/2007, finished May  2010)

    11.  
  11. W. Huang, "Numerical Studies of Ultra-Thin Body SOI MOSFETs," FYP A6152S, Nanyang Technological University, 2006/07.

    12.  
  12. X. Q. Shi and T. Gou, "Numerical Exploration of Multiple-Gate MOSFETs," FYP A6151, Nanyang Technological University, 2006/07.

    13.  
  13. C. Q. Wei, "Advanced MOSFET Noise Compact Modeling," Ph.D. Thesis, Nanyang Technological University (starting 7/2006, finished May  2010)

    14.  
  14. S. H. Lin, "Carbon Nanotube Based Transistor Modeling for Nanoelectronics," Ph.D. Thesis, Nanyang Technological University (starting 1/2006, in progress).

    15.  
  15. G. J. Zhu and F. Li, "Framework Implementation of Design and Optimization of Ultra-Small Transistors," FYP A6099, Nanyang Technological University, 2005/06.

    16.  
  16. S. X. Wang and C. Q. Wei, "Numerical Simulation of Double-Gate MOSFETs," FYP E6098, Nanyang Technological University & Institute of Microelectronics, 2005/06.

    17.  
  17. G. H. Lim, "Development of Statistical Models for Baseband MOSFET Models," M.Eng. Thesis.  (starting July/2005; finished Sep. 2007)

    18.  
  18. G. H. See, "Scalable RF Compact Modeling for Nanometer CMOS Technology," Ph.D. Thesis, Nanyang Technological University (starting 12/2004; finished April 2008).

    19.  
  19. F. Lu and Feng Pan, "Unified Compact Model Implementation for Deep-Submicron MOSFET Circuit Simulation," FYP A6111, Nanyang Technological University, 2004/05.

    20.  
  20. S. Kumar and C. B. Teng, "Statistical Process Control and Monitoring for Deep-Submicron CMOS Technology Using Compact Models and Numerical Simulations," FYP B6110, Nanyang Technological University, 2004/05.

    21.  
  21. R. Selomulya, "Framework Design for Nanometer Technology Development and Transistor Optimization," M.Sc. candidate.  (starting 8/2003, finished 8/2004)

    22.  
  22. K. Chandrasekaran, "Nanoscale Strained-Si/SiGe MOSFET Modeling," Ph.D. Thesis, Nanyang Technological University (starting 7/2002; finished 9/2006).

    23.  
  23. W. Tan, "Technology Prediciton with Semi-Empirical Compact Modeling Approach," M.Sc. Dissertation, Nanyang Technological University (starting 7/2002, finished 6/2003).

    24.  
  24. S. B. Chiah, "Unified AC Charge and DC Current Modeling for Very-Deep-Submicron CMOS Technology," Ph.D. Thesis, Nanyang Technological University (starting 6/2000, thesis submitted 12/2005).

    25.  
  25. H. K. Tay and C. C. Tan, "Compact Model Approach to Statistical Process Control for Deep-Submicron CMOS Technology,"FYP B6085, Nanyang Technological University, 2002/03.

    26.  
  26. J. Wang and Z. Zhao, "Capacitance Modelling and Simulation for Deep-Submicron MOSFETs," FYP B6086, Nanyang Technological University, 2002/03.

    27.  
  27. Y. M. Soh and K. Y. Kam, "TCAD-Synthesis Approach to Deep-Submicron MOSFET Design and Optimization," FYP C6079, Nanyang Technological University, 2000/01. View Report in PDF View Slide in PDF

    28.  
  28. Y. Wang, "Predictive Technology Modeling for Deep-Submicron MOSFET Design," M.Eng. Thesis, Nanyang Technological University (starting 6/1999, completed 6/2001).

    29.  
  29. K. Y. Lim, "Design, Modeling, and Characterization of Submicron MOSFEFs," Ph.D. Thesis, Nanyang Technological University (starting 8/1997, completed 7/2000).

    30.  
  30. C. T. Tan and K. M. Tham, "Design and Optimisation of Ultra-Small Transistors," FYP I6075, Nanyang Technological University, 1998/99.

    31.  
  31. N. Nagappan and S. Pradip, "SUPREM Process Model Parameter Calibration,"FYP I6076, Nanyang Technological University, 1998/99.

    32.  
  32. K. Y. Lim and G. Y. Chong, "Virtual Wafer Fabrication," FYP I6064, Nanyang Technological University, 1996/97.

    33.  
  33. S. C. Tan and S. W. Tan, "Simulated Device Fabrication and Characterization Process," FYP I2141, Nanyang Technological University, 1994/95.