A Simple and Unambiguous Definition of Threshold
Voltage and Its Implications in Deep-Submicron MOS Device Modeling
X. Zhou, Member, IEEE, K. Y. Lim, Student Member,
IEEE, and D. Lim
IEEE Transactions on Electron Devices,
Vol. 46, No. 4, pp. 807-809, April 1999.
(Manuscript received September 8, 1998; revised November 2, 1998)
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Abstract
A new definition of MOSFET threshold voltage is proposed, namely, the
"critical-current at linear-threshold" method, which has a unique solution
and is very simple to measure. This definition gives consistent values
of threshold voltage for different regions of operation at long channel,
and contains the information on short-channel effects at short channel,
which is very useful for deep-submicron MOS device characterization and
modeling. The proposed method effectively removes ambiguity of de
facto industry standard of the constant-current method for MOS threshold
voltage.
References
-
[1] A. Akers and J. J. Sanchez, “Threshold voltage models of short, narrow,
and small geometry MOSFET’s: A review,” Solid-State Electron., vol. 25,
no. 7, pp. 621–641, 1982.
-
[2] J. J. Liou, A. Ortiz-Conde, and F. G. Sanchez, “Extraction of the threshold
voltage of MOSFET’s: An overview,” in Proc. IEEE HKEDM’97, Hong Kong, 1997,
pp. 31–38.
-
[3] Z. X. Yan and M. J. Deen, “Physically-based method for measuring the
threshold voltage of MOSFET’s,” in Proc. Inst. Elect. Eng. G, 1991, vol.
138, no. 3, pp. 351–357.
-
[4] H. S. Wong, M. H. White, T. J. Krutsick, and R. V. Booth, “Modeling
of transconductance degradation and extraction of threshold voltage in
thin oxide MOSFET’s,” Solid-State Electron., vol. 30, no. 9, pp. 953–968,
1987.
-
[5] S. Jain, “Measurement of threshold voltage and channel length of submicron
MOSFET’s,” in Proc. Inst. Elect. Eng. G, 1988, vol. 135, p. 162.
-
[6] X. Zhou, K. Y. Lim, and D. Lim, “A general approach to compact threshold
voltage formulation based on 2-D numerical simulation and experimental
correlation for deep-submicron ULSI technology development,” submitted
for publication.
-
[7] Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. K. Ko, and
Y. C. Cheng, “Threshold voltage model for deep-submicrometer MOSFET’s,”
IEEE Trans. Electron Devices, vol. 40, pp. 86–94, Jan. 1993.
-
[8] K. Y. Lim and X. Zhou, “Modeling of threshold voltage with nonuniform
substrate doping,” in Proc. IEEE ICSE, Malaysia, Nov. 1998, pp. 27–31.
-
[9] X. Zhou, K. Y. Lim, and D. Lim, “A new ‘critical-current at linear-threshold’
method for direct extraction of deep-submicron MOSFET effective channel
length,” submitted for publication.
-
[10] X. Zhou and W. Long, “A novel hetero-material gate (HMG) MOSFET for
deep-submicron ULSI technology,” IEEE Trans. Electron Devices, vol. 45,
pp. 2546–2548, Dec. 1998.
Citation
-
[9] X. Zhou, K. Y. Lim, and D. Lim,
"A new 'Critical-Current at Linear-Threshold' method for direct extraction
of deep-submicron MOSFET effective channel length," IEEE Trans. Electron
Devices, Vol. 46, No. 7, pp. 1492-1494, July 1999.
-
[13] X. Zhou, "Exploring the novel
characteristics of Hetero-Material Gate Field-Effect Transistors (HMGFET's)
with gate-material engineering," IEEE Trans. Electron Devices, Vol. 47,
No. 1, pp. 113-120, Jan. 2000.
-
[2] X. Zhou and K. Y. Lim, "A
novel approach to compact I-V modeling for deep-submicron MOSFET's technology
development with process correlation," Proc. 3rd International Conference
on Modeling and Simulation of Microsystems (MSM2000), San Diego, CA, Mar.
2000, pp. 333-336.
-
[7] K. Y. Lim and X. Zhou, "A physically-based
semi-empirical effective mobility model for MOSFET compact I-V modeling,"
Solid-State Electron., Vol. 45, No. 1, pp. 193-197, Jan. 2001.
-
[10] X. Zhou and K. Y. Lim, "Experimental
determination of electrical, metallurgical, and physical gate lengths of
submicron MOSFET's," Proc. 4th International Conference on Modeling and
Simulation of Microsystems (MSM2001), Hilton Head Island, SC, Mar. 2001,
pp. 44-47.
-
[4] X. Zhou, K. Y. Lim, and W. Qian,
"Threshold voltage definition and extraction for deep-submicron MOSFETs,"
Solid-State Electron., Vol. 45, No. 3, pp. 507-510, Apr. 2001.
-
[8] J.
A. Salcedo, A. Ortiz-Conde, E.J.G. Sanchez, J. Muci, J.J. Liou, and Y.
Yue, "New approach for defining the threshold voltage of MOSFETs,"
IEEE Trans. Electron Devices, Vol. 48, No. 4, pp. 809-813, Apr. 2001.
-
[19] X. Zhou and K. Y. Lim, "Unified
MOSFET compact I-V model formulation through physics-based effective transformation,"
IEEE Trans. Electron Devices, Vol. 48, No. 5, pp. 887-896, May 2001.
-
[17] X. Zhou, S. B. Chiah, K.
Y. Lim, Y. Wang, X. Yu, S. Chwa, A. See, and L. Chan, "Technology-dependent
modeling of deep-submicron MOSFET's and ULSI circuits," (Invited Paper),
Proc. 6th International Conference on Solid-State and Integrated-Circuit
Technology (ICSICT-2001), Shanghai, Oct. 2001, Vol. 2, pp. 855-860.
-
[13] X. Zhou and K. Y. Lim, "De-embedding
length-dependent edge-leakage current in shallow trench isolation submicron
MOSFETs," to appear in Solid-State Electron., 2002.
-
[7] X. Zhou, "Xsim: A compact
model for bridging technology developers and circuit designers," (Invited
Paper), to appear in Proc. 5th International Conference on Modeling and
Simulation of Microsystems (WCM-MSM2002), San Juan, Puerto Rico, Apr. 2002.
-
[13] X. Zhou and K. Y. Lim, "De-embedding
Length-Dependent Edge-Leakage Current in Shallow Trench Isolation Submicron
MOSFETs," Solid-State Electron., Vol. 46, No. 5, pp. 769-772, Apr. 2002.
-
[10] A.
Ortiz-Conde, F. J. García Sáncheza, J. J. Liou, A. Cerdeira,
M. Estradac, and Y. Yue, "A review of recent MOSFET threshold voltage
extraction methods," Microelectronics Reliability, Vol. 42, No. 4-5, pp.
583-596 2002, April-May 2002.
-
[14] M.
Y. Kwong, R. Kasnavi, P. Griffin, J. D. Plummer, R. W. Dutton,
"Impact of lateral source/drain abruptness on device performance," IEEE
Trans. Electron Devices, Vol. 49, No. 11, pp. 1882-1890, Nov. 2002.
-
[11] A.
Chaudhry and M. J. Kumar, "Investigation of the Novel Attributes
of a Fully Depleted Dual-Material Gate SOI MOSFET," IEEE Trans. Electron
Devices, Vol. 51, No. 9, pp. 1463-1467, September 2004.
-
[] G. V. Reddy and M. J. Kumar, "Investigation of the novel attributes
of a single-halo double gate SOI MOSFET: 2D simulation study," Microelectronics
Journal, Vol. 35, No. 9, pp. 761-765, September 2004.
-
[13] G.
Venkateshwar Reddy and M. Jagadesh Kumar, "Investigation of the
novel attributes of a single-halo double gate SOI MOSFET: 2D simulation
study," Microelectronics J., Vol. 35, No. 9, pp. 761-765, 2004.
-
[29] G.
V. Reddy and M. J. Kumar , "A new dual-material double-gate (DMDG)
nanoscale SOI MOSFET - Two-dimensional analytical modeling and simulation,"
IEEE Trans. Nanotechnology, Vol. 4, No. 2, pp. 260-268, Mar. 2005.
-
[] K. Lee, J. H. Kim, and S. Im, "Probing the work function of a
gate metal with a top-gate ZnO-thin-film transistor with a polymer dielectric,"
Appl. Phys. Lett., Vol. 88, No. 2, 023504, Jan. 2006.
-
[] R. Kaur, R. Chaujar, M. Saxena, and R. S. Gupta, "Performance
investigation of 50-nm insulated-shallow-extension gate-stack (ISEGaS)
MOSFET for mixed mode applications," IEEE Trans. Electron Devices, Vol.
54, No. 2, pp. 365-368, Feb. 2007.
-
[45] V.
Venkataraman, S. Nawal, and M. J. Kumar, "Compact Analytical Threshold-Voltage
Model of Nanoscale Fully Depleted Strained-Si on Silicon–Germanium-on-Insulator
(SGOI) MOSFETs," IEEE Trans. Electron Devices, Vol. 54, No. 3, pp. 554-562,
Mar. 2007.
-
[24] T.
K. Chiang and M. L. Chen, "A new analytical threshold voltage model
for symmetrical double-gate MOSFETs with high-k gate dielectrics," Solid-State
Electron., Vol. 51, No. 3, pp. 387-393, Mar. 2007.
-
[18] G. Zhang, Z. Shao, and K. Zhou, "Threshold voltage model of
short-channel FD-SOI MOSFETs with vertical Gaussian profile," IEEE Trans.
Electron Devices, Vol. 55, No. 3, pp. 803-809, Mar. 2008.
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