This project will explore the prediction of new CMOS technology parameters with the aid of a semi-empirical compact model (CM) that has been calibrated to the given (current) technology.  The CM parameters will be extracted from a given technology data and, whenever possible, correlated to process parameters.  Extrapolation to scaled devices will be studied for optimizing the performance with variation of major process parameters.  Numerical devices will be used for verification of the prediction approach.  The knowledge obtained from this project will be directly useful for deep-submicron technology development.

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