As mainstream CMOS technologies continue to scale into the nanometer regime, non-classical structures are emerging, and one of the promising candidates is the ultra-thin body (UTB) Silicon-on-Insulator (SOI) MOSFETs, although its concepts and modeling has started in the 90’s.  From the electrical modeling point of view, it can be built upon existing infrastructure of bulk CMOS compact models, with extension to handle partially-depleted (PD), fully-depleted (FD), and dynamically-depleted (DD) device operations.  A unified approach to modeling PD/FD/DD UTB MOSFET charge and current, combining surface-potential and charge-based formalisms will be adopted to build a compact UTB SOI MOSFET model for circuit simulation.  The main objective is to extend bulk and double-gate MOS compact models to incorporate PD/FD/DD operations in UTB MOSFETs with seamless transition for different mode of operations.  The developed model should be physical and scalable with device geometry and structural parameters.  One special concern for PD-SOI is the modeling of floating-body effect, which will be explored with the subcircuit-expansion approach.  The UTB/SOI modeling is also in line with the generic multiple-gate MOSFET model development.

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