Khee Yong Lim*, Xing Zhou*, and David Lim†
*School of Electrical & Electronic Engineering, Nanyang
Technological University, Nanyang Avenue, Singapore 639798
Fax: (65) 791-2687. Email: exzhou@ntu.edu.sg
†Chartered Semiconductor Manufacturing Ltd., 60 Woodlands
Industrial Park D, Street 2, Singapore 738406
Proc. of the 2nd International Conference on Modeling and Simulation of Microsystems (MSM99)
San Juan, Puerto Rico, U.S.A., April 19-21, 1999, pp. 423-426.
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This paper presents a compact length-dependent saturation current (Idsat)
model for deep-submicron MOSFET’s based on accurate modeling of the threshold
voltage (Vth). A predictive bias-dependent Vth model that relates
to process conditions has been developed [1], [2]. An extension of the
Vth model [1] is used in this work, which consists of only five
important process-dependent parameters and two auxiliary DIBL parameters,
namely, Ns, l, a,
b,
k
and i, j, respectively. Each parameter has its own physical representation
that characterizes the individual short-channel effects. The first parameter
Ns represents an effective vertical channel nonuniform doping
profile, whereas the parameters
k and b
characterize the reverse short channel effect (Vth roll-up).
The normal short channel effect (Vth roll-off) is modeled by
l
and a. The auxiliary parameters i and j are
introduced in this work to fine tune the DIBL dependence, which model the
asymmetric nature of the source and drain depletion region at high Vds
condition. The Vth model requires a five-steps parameter extraction
based on only five sets of measurement data: Vth(Vbs)
at long channel, Vth(Lg, low Vds, high
Vbs), Vth(Lg, low Vds, low
Vbs), Vth(Lg, high Vds,
low Vbs), and Vth(Lg, high Vds,
high Vbs). With additional long-channel Vth(Vbs)
data for different wafers, the Vth model can correlate to process
variables such as Vth adjust implant dose and punchthrough implant
energy.
Once a good Vth model is available, developing an Idsat
model is mainly a matter of mobility and series resistance modeling. The
Idsat model in [3] is employed, combined with our Vth
model to predict experimental data from the same wafer. The Idsat
model considers all the important short-channel effects, which include
mobility degradation, velocity saturation, as well as source/drain series
resistance. The low-field mobility (m0)
and series resistance (Rs) are extracted by fitting to one set
of Idsat versus Lg data at Vds=Vgs=Vdd.
Once these two parameters are determined, a complete compact Idsat
model with drawn gate length (Lg), bias voltages (Vgs,
Vds, Vbs) and process variables (implant dose F
and energy E) as input parameters is available.
The excellent prediction of the Idsat model (lines) to the
experimental data (symbols) has been demonstrated in Figs.1-4. The extracted
empirical correlation between the channel doping parameter (Ns)
and the implant dose and energy (shown in the insets of Figs. 3 and 4)
applies equally well to the saturation current. This work demonstrates
an efficient and accurate approach to modeling deep-submicron MOSFET’s,
which is very useful for reducing experimental wafer spilt-lot and for
process control and optimization.