Khee Yong Lim*, Xing Zhou*, and David Lim†
*School of Electrical & Electronic Engineering, Nanyang
Technological University, Nanyang Avenue, Singapore 639798
Fax: (65) 791-2687. Email: exzhou@ntu.edu.sg
†Chartered Semiconductor Manufacturing Ltd., 60 Woodlands
Industrial Park D, Street 2, Singapore 738406
Fig. 1 Measured (symbols) and modeled (lines) saturation current vs. gate length for different supply voltage Vdd (with Vgs = Vds = Vdd). Only the Vdd = 2.5 V data are used for µ0 and Rs extraction. All others are predictions by the model.
Fig. 2 Measured (symbols) and modeled (lines) saturation current vs. gate length for different substrate bias Vbs. The Vbs dependency is modeled by the parameters in the Vth model.
Fig. 3 Measured (symbols) and modeled (lines) saturation current vs. gate length for different Vth-adjustment implant dose F. The inset shows the extracted linear correlation between Ns and F extracted from the Vth model.
Fig. 4 Measured (symbols) and modeled (lines) saturation current
vs. gate length for different punchthrough implant energy E. The
inset shows the extracted linear correlation between Ns
and E extracted from the Vth model.