As conventional bulk-CMOS scaling is approaching its physical limit, alternative device structures are emerging, such as ultra-thin-body (UTB) SOI and double-gate (DG) MOSFETs.  This project is directed towards comparing various device structures and their performance through numerical simulations.  By design of experiment (DOE) of variations in the device geometry, layer thickness, and doping, device performance parameters, such as on/off current, subthreshold slope, intrinsic gain, etc., can be obtained and compared.  Device operations, such as common/independent biasing of DG and partially/fully-depleted SOI, can also be studies and compared.  The project gives the student an opportunity to learn device physics through practical DOE and performance evaluations.