IEEE Transactions on Electron Devices, Vol. 53, No. 12, pp. 3110-3117, Dec. 2006
(Manuscript received June 1, 2006; revised  September 1, 2006.)

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A new technique for calculating surface and interface potentials in heterostructure MOSFETs such as strained-Si/SiGe using an internal iteration approach is presented.  It is based on the unified regional approach with coupled iterative potential solutions at the surface and heterostructure interface, and it has been applied to modeling strained-Si/SiGe MOSFETs charge and capacitance in all bias regions, scalable for Ge mole fraction, strained-Si and SiGe layer thicknesses and doping.  The formulations are shown for a buried-channel nMOSFET, and the approach to the solutions is generic to all heterostructures which exhibit confinement of carriers at the different interfaces.

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