IEEE Transactions on Electron Devices, Vol. 55, No. 2, pp. 624-631, Feb. 2008.
(Manuscript received July 5, 2007; revised  October 15, 2007.)

Copyright Notice

© 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

This paper presents a new concept for the MOSFET saturation voltages at the drain and source sides referenced to bulk, and applies them to the popularly used smoothing functions for the effective drain–source voltage (V_ds,eff).  The proposed model not only builds in physically all the terminal-bias variations, but is also extended to include source/drain asymmetry in real devices in a single core compact model.  The new model resolves a key bottleneck in existing models for passing the Gummel symmetry test (GST) in higher order derivatives, which has to be traded off for the geometry-dependent Vds,eff smoothing parameter.  The complete drain-current model, including the effects of velocity saturation and overshoot as well as source/drain series resistance, has also been reformulated with the same “bulk-referencing” concept.  It is shown that the proposed model passes the GST in all higher order derivatives without any constraint on the value of the smoothing parameter.  It also demonstrates potential extension to modeling asymmetric MOSFETs, which is becoming an important model capability.

• [1] [Online]. Available:

http://ray.eeel.nist.gov/modval/database/contents/reports/micromosfet/standard.html
• [2] C. C. McAndrew, “Validation of MOSFET model source–drain symmetry,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2202–2206, Sep. 2006.
• [3] K. Joardar, K. K. Gullapalli, C. C. McAndrew, M. E. Burnham, and A. Wild, “An improved MOSFET model for circuit simulation,” IEEE Trans. Electron Devices, vol. 45, no. 1, pp. 134–148, Jan. 1998.
• [4] [Online]. Available: http://www-device.eecs.berkeley.edu/%7Ebsim3/
• [5] [Online]. Available: http://pspmodel.asu.edu/
• [6] P. Bendix, P. Rakers, P. Wagh, L. Lemaitre, W. Grabinski, C. C. McAndrew, X. Gu, and G. Gildenblat, “RF distortion analysis with compact MOSFET models,” in Proc. CICC, Oct. 2004, pp. 9–12.
• [7] X. Zhou and K. Y. Lim, “Unified MOSFET compact I V model formulation through physics-based effective transformation,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 887–896, May 2001.
• [8] C. G. Sodini, P. K. Ko, and J. L. Moll, “The effect of high fields on MOS device and circuit performance,” IEEE Trans. Electron Devices, vol. ED-31, no. 10, pp. 1386–1396, Oct. 1984.
• [9] T. L. Chen and G. Gildenblat, “Symmetric bulk charge linearisation in charge-sheet MOSFET model,” Electronics Lett., vol. 37, no. 12, pp. 791–793, 2001.
• [10] S. B. Chiah, X. Zhou, K. Y. Lim, L. Chan, and S. Chu, “Source–drain symmetry in unified regional MOSFET model,” IEEE Electron Device Lett., vol. 25, no. 5, pp. 311–313, May 2004.
• [11] C. C. McAndrew, “Useful numerical techniques for compact modeling,” in Proc. 2002 Int’l Conf. Microelectronic Test Structures, 2002.
• [12] X. Zhou, K. Chandrasekaran, S. B. Chiah, W. Z. Shangguan, Z. M. Zhu, G. H. See, S. M. Pandey, G. H. Lim, S. Rustagi, M. Cheng, S. Chu, and L.-C. Hsia, “Unified approach to bulk/SOI/UTB/s-DG MOSFET compact modeling,” in Proc. NSTI Nanotech 2006, vol. 3, pp. 652–657.
• [13] S. B. Chiah, “Unified AC Charge and DC Current Modeling for Very-Deep-Submicron CMOS Technology,” Ph.D. thesis, Nanyang Technological Univ., Singapore, 2007.
• [14] L. F. Wagner and C. M. Olsen, “LINFET: A BSIM class FET model with smooth derivatives at Vds=0,” in Proc. NSTI Nanotech 2007, vol. 3, pp. 629–632.
• [15] G. H. See, X. Zhou, K. Chandrasekaran, S. B. Chiah, Z. M. Zhu, G. H. Lim, C. Q. Wei, S. H. Lin, and G. J. Zhu, “Gummel symmetry with higher-order derivatives in MOSFET compact models,” in Proc. NSTI Nanotech 2007, vol. 3, pp. 613–616.
• [16] T. Horiuchi, T. Homma, Y. Murao, and K. Okumura, “An asymmetric sidewall process for high performance LDD MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, no. 2, pp. 186–190, Feb. 1994.
• [17] J. F. Chen, J. Tao, P. Fang, and C. Hu “0.35-?m asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology,” IEEE Electron Device Lett., vol. 19, no. 7, pp. 216–218, July 1998.
• [18] T. N. Buti, S. Ogura, N. Rovedo, K. Tobimatsu, and C. F. Codella, “Asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half micron n-MOSFET design for reliability and performance,” in IEDM Tech. Dig., 1989, pp. 617–620.
• [19] W. Long and K. K. Chin, “Dual material gate field effect transistor (DMGFET),” in IEDM Tech. Dig., 1997, pp. 549–552.
• [20] X. Zhou, “Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFET’s) with gate-material engineering,” IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 113–120, Jan. 2000.
• [21] J. P. Kim, W. Y. Choi, J. Y. Song, S. W. Kim, J. D. Lee, and B.-G. Park, “Design and fabrication of asymmetric MOSFETs using a novel self-aligned structure,” IEEE Trans. Electron Devices, vol. 54, no. 11, pp. 2969–2974, Nov. 2007.
• [22] K. Y. Lim and X. Zhou, “An analytical effective channel-length modulation model for velocity overshoot in submicron MOSFETs based on energy-balance formulation,” Microelectron. Reliab., vol. 42, no. 12, pp. 1857–1864, Dec. 2002.