This project aims at aiding technology development of nanoscale CMOS for process control and monitoring as well as statistical best/worse-case analysis.  Due to inevitable process fluctuations, such as gate-oxide nonuniformity, poly-gate and LDD spacer lithography and etching, channel and source/drain doping variation, device characteristics vary from lot to lot, wafer to wafer, die to die.  Characterizing these statistical variations and capturing them in a compact model for circuit designers to perform best/worse-case analysis are essential for reducing design margins and producing reliable designs.  The project involves characterizing wafers and collecting statistical MOSFET parameters, and subsequently mapping these parameters into a corresponding set of model parameters, hence creating a statistical Baseband BSIM model.  This project involves device characterization, statistical analysis, compact modeling for circuit simulation.  The developed methodology will have important applications for wafer foundries as well as circuit design houses.

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