Proceedings of the 9th International Symposium on Integrated Circuits, Devices & Systems (ISIC2001)

September 3-5, 2001, Singapore, pp. 238-241.

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In this paper, the gate-voltage-dependent series resistance (R_sd) trend is extracted from two MEDICI-simulated MOSFET devices, one with LDD extension and the other without LDD extension.  Three sets of MOSFET’s of varying gate length are designed with different LDD extension structures for I_ds - V_gs prediction.  The results confirm the R_sd behavior trend in deep-submicron MOSFET’s as well as the compact model and help to relate the compact model parameters to the physical structure of the MOSFET’s, which can be further correlated to true process variables that determine the device structure.

• [1] E. Gondro, F. Schuler, and P. Klein, “A physics bused resistance model of the overlap regions in LDD-MOS-FETs,” Proc. SISPAD, Leuven, Belgium, pp. 267–270,1998.
• [2] E. Gondro, “An improved bias dependent series resistance description for MOS models,” Compact Model Council meeting, Santa Clara, USA, May 15, 1998.
• [3] K. Y. Lim and X. Zhou, “A physically-based semi-empirical series resistance model for deep-submicron MOSFET I-V modeling,” IEEE Trans. Electron Devices, vol. 47, pp. 1300– 1302, June 2000.
• [4] X. Zhou and K. Y. Lim, “Unified MOSFET compact I-V model formulation through physics-based effective transformation,” IEEE Trans. Electron Devices, vol. 48, pp. 887–896, May 2001.