MSM2005

Unified Regional Charge-based Versus Surface-potential-based Compact Modeling Approaches
Xing Zhou*, Siau Ben Chiah*, Karthik Chandrasekaran*, Guan Huei See*, Wangzuo Shangguan*,
Shesh Mani Pandey**, Michael Cheng**, Sanford Chu**, and Liang-Choo Hsia**

* School of Electrical & Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798
Phone: (65) 6790-4532. Fax: (65) 6791-2687. Email: exzhou@ntu.edu.sg
** Chartered Semiconductor Manufacturing Ltd, 60 Woodlands Industrial Park D, St. 2, Singapore 738406

Proc. of the NSTI Nanotech 2005 (WCM-MSM2005)

Anaheim, CA, May 8-12, 2005, WCM, pp. 25-30.

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Abstract

This paper outlines the key features and advantages of the unified regional charge-based approach to MOSFET compact charge modeling in comparison with surface-potential-based approaches. Physical piecewise solutions are regionally derived from Pao-Sah equation, in which bulk charge is modeled by direct addition of accumulation and depletion charges based on the unified regional (source-end) surface potential. Drain-bias-dependent bulk and inversion charges are modeled with the unified regional charges in strong inversion using the non-pinned surface potential. Results have been compared with the iterative solutions and validated with numerical data. It has been extended to poly-accumulation/depletion/inversion effects with explicitly coupled quantum-mechanical effect as well as to strained-Si MOSFETs within the same unified model.

References

[1] H. Pao and C.-T. Sah, Solid-State Electron. 9, 927 (1966).
[2] C.-T. Sah and H. Pao, IEEE Trans. Electron Devices ED-13, 393 (1966).
[3] C. C. McAndrew and J. J. Victory, IEEE Trans. Electron Devices 49, 72 (2002).
[4] C.-T. Sah, private communications; also, B. B. Jie and C.-T. Sah, WCM-Nanotech2005, Anaheim, 2005.
[5] M. Miura-Mattausch et al., IEEE Trans. CAD 15, 1 (1996).
[6] R. Rios et al., Proc. IEDM, San Francisco, 2004, p. 755.
[7] R. van Langevelde et al., Proc. WCM-MSM2004, Boston, 2004, vol. 2, p. 60.
[8] T.-L. Chen and G. Gildenblat, Solid-State Electron. 45, 335 (2001).
[9] G. Gildenblat et al., IEEE J. Solid-State Circuits 39, 1394 (2004).
[10] J. He et al., Proc. WCM-Nanotech2003, San Francisco, 2003, vol. 2, p. 302.
[11] R. van Langevelde and F. M. Klaassen, Solid-State Electron. 44, 409 (2000).
[12] G. H. See, S. B. Chiah et al., Proc. WCM-Nanotech2005, Anaheim, 2005.
[13] K. Y. Lim and X. Zhou, Microelectronic Reliab. 42, 1857 (2002).
[14] P. K. Ko, in VLSI Electronics: Microstructure Science, Academic, vol. 18, 1987.
[15] M. Miura-Mattausch and H. Jaocobs, Jpn. J. Phys. 29, L2279 (1990).
[16] X. Zhou et al., Proc. WCM-MSM2004, Boston, 2004, vol. 2, p. 74.
[17] L. Ge and J. G. Fossum, IEEE Trans. Electron Devices 48, 2074 (2001).
[18] J. Watts et al., “Advanced compact models for MOSFETs,” Proc. WCM-Nanotech2005, Anaheim, 2005.
[19] K. Joardar et al., IEEE Trans. Electron Devices 45, 134 (1998).
[20] R. Rios, private communications; also [18].
[21] D. E. Ward and R. W. Dutton, IEEE J. Solid-State Circuits SSC-13, 703 (1978).
[22] J. R. Brews, Solid-State Electron. 21, 345 (1978).
[23] N. Arora, MOSFET Models for VLSI Circuit Simulation? Theory and Practice, Springer-Verlag, 1993.
[24] X. Zhou et al., Proc. IWCM2005, Shanghai, 2005, p. 13.
[25] S. B. Chiah et al., submitted for publication.
[26] M. J. van Dort et al., Solid-State Electron. 37, 411 (1994).
[27] K. Chandrasekaran et al., submitted for publication.

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