This project is directed towards the development and implementation of semi-empirical compact models for the design and optimization of ultra-small transistors in the context of the 0.25/0.18-µm technology at Chartered Semiconductor Manufacturing (CSM). The objective is to link device performance parameters to process variables through a combined numerical simulation, compact modeling, and experimental correlation. This approach can provide a guide to process and device engineers in new technology development and advanced transistor design as well as a first attempt at process control and transistor optimization.

  First-year presentation

  M.Eng. thesis
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