Mixed-Signal Multi-Level Simulation of VLSI Circuits (XSIM)

Introduction | Xsim | Brochure || DOUST

Related Publications

  1. X. Zhou, "The Missing Link to Seamless Simulation," (Invited Feature Article), IEEE Circuits Devices Mag., Vol. 19, No. 3, pp. 9-17, May 2003. Download PDF

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  2. X. Zhou, "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," (Invited Plenary Paper), Proc. of the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002), Wroclaw, Poland, June 20-22, 2002, pp. 27-31. Download PDF View Slides

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  3. X. Zhou, "Multi-Level Modeling of Deep-Submicron MOSFETs and ULSI Circuits," (Invited Paper), Proc. of the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002), Wroclaw, Poland, June 20-22, 2002, pp. 39-44. Download PDF View Slides

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  4. X. Zhou, "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," (Invited Paper), Proc. of the National Seminar on VLSI: Systems, Design and Technology (VSDT2000), Indian Institute of Technology, Bombay, December 10-11, 2000, pp. 10-15. Download PDF View Slides

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  5. T. Tang and X. Zhou, "Multi-Level Digital/Mixed-Signal Simulation with Automatic Circuit Partition and Dynamic Delay Calculation," J. Modeling Simulation Microsystems (JMSM), Vol. 1, No. 2, pp. 83-89, December 1999. Download PDF

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  6. S. S. Rofail, K. S. Yeo, K. W. Chew, X. Zhou, and T. Tang, "An Experimentally-Based DC Model for the Bi-MOS Structure and Its Adaptation to a Circuit Simulation Environment," Proc. of the IEEE Canadian Conference on Electrical and Computer Engineering (CCECE98), Waterloo, Canada, May 24-28, 1998, Vol. 1, pp. 37-40. Download PDF View Citation

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  7. T. Tang and X. Zhou, "A Dynamic Timing Delay for Accurate Gate-Level Circuit Simulation," Proc. of the 39th Midwest Symposium on Circuits and Systems (MWSCAS-96), Ames, Iowa, August 18-21, 1996, pp. 325-327. Download PDF

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  8. T. Tang and X. Zhou, "Accurate Timing Simulation of Mixed-Signal Circuits with a Dynamic Delay Model," Proc. of the International Workshop on Computer-Aided Design, Test, and Evaluation for Dependability (CADTED), Beijing, July 2-3, 1996, pp. 309-311. Download PDF

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  9. X. Zhou and T. Tang, "Modelling and Simulation of GaAs High-Speed HEMT, HBT, and MESFET Analogue/Digital Circuits," Proc. of the 7th MINDEF-NTU Joint R&D Seminar, Nanyang Technological University, Singapore, January 12, 1996, pp. 77-83. Download PDF

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  10. T. Tang, X. Zhou, and C. C. Jong, "Mixed-Mode Simulation of High-Speed HFET Logic Circuit," Proc. of the 6th International Symposium on IC Technology, Systems & Applications (ISIC-95), Singapore, September 6-8, 1995, pp. 510-514.

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  11. X. Zhou and T. Tang, "Multi-Level Modelling of GaAs High-Speed Digital Circuits," The EEE Journal, School of Electrical and Electronic Engineering, Nanyang Technological University, Vol. 7, No. 1, pp. 58-64, July 1995.

Related Presentations

  1. "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," Research Seminar, Technical University of Munich, Germany, Oct. 13, 2009.

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  2. "The Missing Link to Seamless Simulation," Invited Talk (IEEE EDS Distinguished Lecture Mini-colloquium), 3rd Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT-Singapore), Singapore, October 15, 2003.

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  3. "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," Invited Talk, Intel Corp., Santa Clara, CA, February 28, 2003.

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  4. "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," Invited Talk (COE Visiting Professor), Research Center for Nanodevices and Systems, Hiroshima University, Japan, January 28, 2003.

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  5. "Multi-Level Modeling of Deep-Submicron CMOS ULSI Systems," 1-Day Short Course, organized by Center for Continuing Education, Nanyang Technological University, September 2, 2002. (Course Brochure)

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  6. "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," Invited Plenary Talk (IEEE EDS Distinguished Lecturer Program), the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002), Wroclaw, Poland, June 21, 2002.

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  7. "Multi-Level Modeling of Deep-Submicron MOSFETs and ULSI Circuits," (Invited Paper), the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002), Wroclaw, Poland, June 20, 2002.

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  8. "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," Invited Talk, Motorola, Geneva, Switzerland, June 17, 2002.

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  9. "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," Invited Talk (IEEE EDS Distinguished Lecturer Program), National Seminar on VLSI: Systems, Design and Technology (VSDT2000), Indian Institute of Technology, Bombay, December 10, 2000. View Slides

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  10. "Mixed-Signal Multi-Level Circuit Simulation with a Dynamic Delay Model," IC CAD Seminar, Nanyang Technological University, October 17, 1996. View Slides

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  11. "A Dynamic Timing Delay for Accurate Gate-Level Circuit Simulation," the 39th Midwest Symposium on Circuits and Systems (MWSCAS-96), Ames, Iowa, August 19, 1996. Download PDF

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  12. "Mixed Analog-Digital Circuit Simulation: An Implicit Mixed-Mode Solution,"Technical Excellence Committee Seminar (1-day in-house course), Thomson Multimedia Pte. Ltd., Singapore, April 19, 1996. View Slides

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  13. "Implicit Mixed-Mode Circuit Simulation," Microelectronics Center Seminar, NanyangTechnological University, October 9, 1992.

Related Theses

  1. F. Lu and Feng Pan, "Unified Compact Model Implementation for Deep-Submicron MOSFET Circuit Simulation," FYP A6111, Nanyang Technological University, 2004/05.

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  2. Tianwen Tang, "Mixed-Mode Analog-Digital Circuit Simulation," M.Eng. Thesis, Nanyang Technological University, 1997.

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  3. L. T. Lam and H. C. Ng, "Circuit Modeling and Parameter Extraction for MMIC Applications," FYP I6063, Nanyang Technological University, 1996/97.

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  4. K. C. Ng and M. H. Ng, "Library Development for Mixed Analog–Digital Circuit Simulation," FYP 6062, Nanyang Technological University, 1996/97.

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  5. C. K. Hung and C. S. Kang, "A Critical Study of SPICE Models for Digital and Analog Circuit Simulation," FYP I6079, Nanyang Technological University, 1995/96.

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  6. T. K. Chew and K. K. Chia, "SPICE Model Implimentation for Circuit Simulation," FYP 2140, Nanyang Technological University, 1994/95.

Citations

  1. S. S. Rofail, K.-S.Yeo, and K.-W. Chew, "DC model for BiMOS structure and its adaptation to a circuit simulation environment," IEE Proc. - Circuits, Devices and Systems, Vol. 146, No. 2 , pp. 83-89, April 1999. Download PDF