CADTED

Accurate Timing Simulation of Mixed-Signal Circuits with a Dynamic Delay Model

Tianwen Tang and Xing Zhou

School of Electrical and Electronic Engineering, Nanyang Technological University
Nanyang Avenue, Singapore 639798, Republic of Singapore

Proc. of the International Workshop on Computer-Aided Design, Test, and Evaluation for Dependability (CADTED)

Beijing, July 2-3, 1996, pp. 309-311.

Copyright Notice

© 1996 International Academic Publishers. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from International Academic Publishers.

Abstract

A dynamic delay model is described and implemented in a single-engine multi-level circuit simulator. It is demonstrated that the model provides near circuit-level accuracy with gate-level speed, and is useful for accurate timing simulation of digital and mixed-signal integrated circuits.

References

[1] L. W. Nagel, “SPICE2: A Complete Program to Simulate Semiconductor Circuits,” Memorandum ERL-M520, University of California, Berkeley, May 1975.
[2] X. Zhou and T. Tang, “Multi-Level Modelling of GaAs High-Speed Digital Circuits,” The EEE Journal, School of Electrical and Electronic Engineering, Nanyang Technological University, Vol. 7, No. 1, pp. 58–64, July 1995.
[3] T. Tang and X. Zhou, “A Dynamic Delay Model for Mixed Gate/Circuit-Level Simulation of VLSI Circuits,” submitted to IEEE Trans. CAD, 1995.

Citation

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