This thesis documents the development of a dynamic-delay model and its implementation in a single-engine mixed-mode simulator with a unified data structure. It is based on electrical (circuit-level) matrix solution, with event-driven (logic-level) techniques as accelerations for simulating digital and mixed analog-digital circuits. The key to its automatic circuit partitioning and dynamic mode switching capabilities is based on the subcircuit expansion approach. It is demonstrated that the developed delay algorithm provides near circuit-level accuracy with comparable speed to other unit-delay models.

A heterostructure field-effect transistor (HFET) model based on the AIM-Spice universal HFET model is implemented in the simulator. This model has been used to construct HFET E/D logic gates for testing the dynamic delay model.

Based on the subcircuit expansion method, a hierarchical probing at various levels is implemented. It allows certain variables to be probed/plotted from the very top level through gate and transistor levels down to the internal subcircuit element of a transistor.

  M.Eng. thesis
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