Proc. of the 39th Midwest Symposium on Circuits and Systems (MWSCAS-96)

Ames, Iowa, August 18-21, 1996, pp. 325-327.

Copyright Notice

© 1997 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

A dynamic delay model, which includes the nonlinear loading effect, the effects of the input transition time and the multiple-input triggering, is proposed for the gate-level timing simulation. It is shown that the developed delay model gives near circuit-level accuracy with comparable speed to other common delay models.

• [1] Z. Wang and P. M. Maurer, “Techniques for Unit-Delay Compiled Simulation,” Proc. 27th Design Automation Conf., pp. 480–484, 1990.
• [2] Y. S. Lee and P. M. Maurer, “Two New Techniques for Multi-Delay Compiled-Code Logic Simulation,” Proc. 29th Design Automation Conf., pp. 420–423, 1992.
• [3] S. Rusu, “Advanced Timing Modeling for VLSI Design,” Proc. EDA&T’94, pp. 223–230, 1994.
• [4] D. Baylor and N. Deo, “Synthesis Sets Timing for Submicron,” Proc. EDA & ASICs, Electronic Engineering Times, 1994.
• [5] A. Davis, “Implicit Mixed-Mode Simulation of VLSI Circuits,” Ph.D. Thesis, University of Rochester, Rochester, New York, 1991.

• X. Zhou and T. Tang, "Multi-level modelling of GaAs high-speed digital circuits," The EEE Journal, School of Electrical and Electronic Engineering, Nanyang Technological University, Vol. 7, No. 1, pp. 58-64, July 1995.
• [3] T. Tang and X. Zhou, "Accurate timing simulation of mixed-signal circuits with a dynamic delay model," Proc. International Workshop on Computer-Aided Design, Test, and Evaluation for Dependability (CADTED), Beijing, July 1996, pp. 309-311.

1. [1] T. Tang and X. Zhou, "Multi-level digital/mixed-signal simulation with automatic circuit partition and dynamic delay calculation," J. Modeling Simulation Microsystems (JMSM), Vol. 1, No. 2, pp. 83-89, Dec. 1999.
2. [4] X. Zhou, "Mixed-signal multi-level circuit simulation: An implicit mixed-mode solution," (Invited Paper), Proc. National Seminar on VLSI: Systems, Design and Technology (VSDT2000), Indian Institute of Technology, Bombay, India, Dec. 2000, pp. 10-15.
3. [23] X. Zhou, S. B. Chiah, K. Y. Lim, Y. Wang, X. Yu, S. Chwa, A. See, and L. Chan, "Technology-dependent modeling of deep-submicron MOSFET's and ULSI circuits," (Invited Paper), Proc. 6th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT-2001), Shanghai, Oct. 2001, Vol. 2, pp. 855-860.
4. [4] X. Zhou, "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," (Invited Plenary Paper), Proc. of the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002), Wroclaw, Poland, June 2002, pp. 27-31.

Session MP1.2 (search Zhou)
IEL Citation