Proc. of the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002)

Wroclaw, Poland, June 20-22, 2002, pp. 27-31.

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A unified and consistent approach to multi-level simulation of mixed-signal VLSI circuits is presented.  It is based on the subcircuit expansion approach, in which digital gates have a dual-representation at the logic and circuit levels.  Dynamic circuit partitioning and mode switching are achieved with the single-engine simulator.  A dynamic-delay model is described for gate-level timing simulation, which includes the effects of nonlinear capacitive loading, input transition time, and multiple-input triggering.  It is shown that the approach provides near circuit-level accuracy with gate-level speed and is useful for accurate timing simulation of digital and mixed-signal VLSI circuits.  A block-level representation for analog circuit acceleration is proposed.  The proposed methodology will prove to be very useful for mixed-signal circuit design in the deep-submicron (DSM) technology era.

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