on Pages: 325 - 327 vol.1

This Conference was Held : 18-21 Aug. 1996

1996

Vol. 1

ISBN: 0-7803-3636-4

IEEE Catalog Number: 96CH35995
Total Pages: 3 vol. xxxv+1439
References Cited: 5
Accession Number: 5602455

A dynamic delay model, which includes the nonlinear loading effect, the effects of the input transition time and the multiple-input triggering, is proposed for the gate-level timing simulation. It is shown that the developed delay model gives near circuit-level accuracy with comparable speed to other common delay models.

circuit analysis computing; dynamic timing delay; gate-level circuit simulation; dynamic delay model; nonlinear loading effect; input transition time; multiple-input triggering; gate-level timing simulation