Proc. of the National Seminar on VLSI: Systems, Design and Technology (VSDT2000)

Indian Institute of Technology, Bombay, India, December 10-11, 2000, pp. 10-15.

Copyright Notice

© Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from copyright owner.

A unified and consistent approach to multi-level simulation of mixed-signal VLSI circuits is presented.  It is based on the subcircuit expansion approach, in which digital gates have a dual-representation at the logic and circuit levels.  Dynamic circuit partitioning and mode switching are achieved with the single-engine simulator.  A dynamic-delay model is described for gate-level timing simulation, which includes the effects of nonlinear capacitive loading, input transition time, and multiple-input triggering.  It is shown that the approach provides near circuit-level accuracy with gate-level speed and is useful for accurate timing simulation of digital and mixed-signal VLSI circuits.  A block-level representation for analog circuit acceleration is proposed.  The proposed methodology will prove to be very useful for mixed-signal circuit design in the deep-submicron (DSM) technology era.

• [1] A. T. Davis, “Implicit Mixed-Mode Simulation of VLSI Circuits,” Ph.D. thesis, Univ. of Rochester, NY, 1990.
• [2] A. T. Davis, “A Vector Approach to Sparse Nodal Admittance Matrices,” Proc. 30th Midwest Symposium on Circuits and Systems, Aug. 1987.
• [3] T. Tang and X. Zhou, “Multi-Level Digital/ Mixed-Signal Simulation with Automatic Circuit Partition and Dynamic Delay Calculation,” J. Modeling and Simulation of Microsystems, Vol. 1, No. 2, pp. 83–89, 1999.
• [4] T. Tang and X. Zhou, “A Dynamic Timing Delay for Accurate Gate-Level Circuit Simulation,” Proc. 39th Midwest Symposium on Circuits and Systems, Iowa, Aug. 1996, pp. 325–327.
• [5] T. Tang, “Mixed-Mode Analog–Digital Circuit Simulation,” M.Eng. thesis, Nanyang Technological University, Singapore, 1997.
• [6] X. Zhou, K. Y. Lim, and D. Lim, “A General Approach to Compact Threshold Voltage Formulation Based on 2-D Numerical Simulation and Experimental Correlation for Deep-Submicron ULSI Technology Development,” IEEE Trans. Electron Devices, Vol. 47, No. 1, pp. 214–221, 2000.
• [7] X. Zhou and K. Y. Lim, “Unified MOSFET Compact Model I-V Formulation Through Physics-Based Effective Transformation,” to appear in IEEE Trans. Electron Devices.

1. [24] X. Zhou, S. B. Chiah, K. Y. Lim, Y. Wang, X. Yu, S. Chwa, A. See, and L. Chan, "Technology-dependent modeling of deep-submicron MOSFET's and ULSI circuits," (Invited Paper), Proc. 6th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT-2001), Shanghai, Oct. 2001, Vol. 2, pp. 855-860.
2. [7] X. Zhou, "Multi-Level Modeling of Deep-Submicron MOSFETs and ULSI Circuits," (Invited Paper), Proc. of the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002), Wroclaw, Poland, June 2002, pp. 39-44.