Mixed-Signal Multi-Level Circuit Simulation:
An Implicit Mixed-Mode Solution

Xing Zhou
School of Electrical & Electronic Engineering
Nanyang Technological University
Nanyang Avenue, Singapore 639798
Email: exzhou@ntu.edu.sg

(Invited Paper - IEEE EDS Distinguished Lecturer Program)

Figures

Fig. 1 | Fig. 2 | Fig. 3 | Fig. 4 | Fig. 5

(a) (b)

Fig. 1 A string of gates (a) driven by an analog stimulus, which can be conceptually partitioned into circuit/gate level (b).

Fig. 2 Subcircuit expansion approach to multi-level logic/transistor modeling.

Fig. 3 Logic block equivalent circuit, including A/D and D/A converters.

Fig. 4 Delay parameters vs. loading capacitance at two input transition times for single-/all-input triggering.

Fig. 5 Multi-level representation of devices/circuits/subsystems, each level having two consistent representations.