Proc. of the 6th International Symposium on IC Technology, Systems & Applications (ISIC-95)

Singapore, September 6-8, 1995, pp. 510-514.

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This paper reports a mixed-mode simulation method for heterostructure field-effect transistor E/D logic circuit based on the universal charge control model. The universal charge control model can correctly predict the performance of the heterostrcuture field-effect transistor at the electrical level, while the gate-level equivalent model can speed up simulation significantly. As we know, circuit simulation is a trade-off between accuracy and CPU time. In this paper, we show that this trade-off is achieved by an "implicit" mixed-mode solution: the switching between circuit-level and gate-level simulation is done dynamically at run time, based on the quality of the input signal of a logic element. The result is very close to that of a full analog simulation but with less cost.

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