Steering Committee Organization Team Members Schedule
Space Segment Ground Segment Launch Segment
Space Segment
(a) Bus:
(b) Payload:

Parallel Processing Unit (PPU)
(Secondary Mission Payload)

The Parallel Processing Unit (PPU) is a Secondary payload onboard XSAT micro-satellite. It is an software payload to demonstrate an enabling technology for performing high performance parallel computing reliably onboard the satellite, employing solely COTS technologies. It is a suitable computing platform for low cost small satellite missions.

Specifically for the XSAT application, PPU enables the real time processing and extraction of desired information from the IRIS 80Mbps multi-spectral camera payload; and provides an efficient data parallelism platform for performing image classification, segmentation and compression of the captured image data. Such capability allows the XSAT mission to support a new class of remote sensing applications thought impossible for low cost small satellites (e.g. continuous surveillance or disaster monitoring). Onboard image processing done to extract useful information out of the IRIS multi-spectral images help to reduce the volume of data required to be stored onboard or downloaded to the ground processing station. The factor for data reduction effectively translates to a reduction in memory and communication downlink requirements by the same factor.

The system architecture of the PPU is described as follows.

It consists of two interconnected Actel FPGA hubs. Each FPGA is a one-time programmable (OTP) chip utilizing anti-fuse technology. This makes it highly resistant to unrecoverable errors in logic caused by radiation effects. Each FPGA hub hosts ten processing nodes (PNs), each consisting of one StrongArm SA1110 (@206MHz) processor and 64MB of Samsung  SDRAM. The FPGAs are connected to two pairs of three Atmel 4MB serial flash chips, which contain the bootload, OS kernel and filesystem images used to boot the processing nodes (PNs). Triple voting is implemented on all data read from the flash memory devices. This lets us operate even if one of the flash memory chips is corrupted due to a single event upset (SEU).

Two Infineon C515C processors with an integrated CAN controller are used to interface the PPU to the XSat CAN bus. The C515C processors are designed to have the capability to re-program the FPGA flash memory, permitting us to reconfigure the system in space.

The PPU is also connected to the 2GB mass storage system (RAMDISK) using high speed low-voltage differential signaling scheme (LVDS), via which image data from the IRIS payload or uploaded code are transferred. An overview of the hardware architecture of the PPU is as shown in figure 1.

Figure 1: PPU Hardware Architecture

It can be noticed that the PPU loosely resembles a cluster-based computing system This means that some PNs can fail but the PPU can still operate. As each FPGA has its own communication links to the satellite bus and the mass storage system, PPU operation can continue even if one FPGA was to fail, but at reduced computation performance. In addition, the use of a commercial operating system like the Linux OS for the StrongArm processors offers the benefit that the users can utilize readily available open source software tools for development.

The programmable flexibility of the computing payload qualifies it as a software payload, allowing new codes and applications to be uploaded at any part of the mission phase. The provision of a familiar Linux code development and debugging platform for application developers makes it possible for even interested third party to independently develop codes for execution onboard XSAT.

The preliminary specifications of the PPU payload are listed in the following table: These figures are subject to change as the development progresses.

The key specifications for PPU are:

800g (max)
300 x 200 x 25 mm
Power consumption
20 watt (max)
Temperature (operating)
0°  to 50°C