Compact Model Application to Logic/Circuit Design of Futuristic Probabilistic-CMOS

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Related Publications

  1. Z. H. Chen, X. Zhou, Y. Z. Hu, and M. K. Srikanth, "Neutral Interface Traps for Negative Bias Temperature Instability," Proc. of the 2011 IEEE Reliability Physics Symposium (IRPS2011), Monterey, CA, Apr. 2011, pp. 913-914.

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  3. Z. H. Chen, X. Zhou, G. J. Zhu, and S. H. Lin, "Interface-Trap Modeling for Silicon-Nanowire MOSFETs," Proc. of the 2010 IEEE Reliability Physics Symposium (IRPS2010), Anaheim, CA, May 2010, pp. 977-980.

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  5. X. Zhou, G. J. Zhu, M. K. Srikanth, S. H. Lin, Z. H. Chen, J. B. Zhang, and C. Q. Wei, "A Unified Compact Model for Emerging DG FinFETs and GAA Nanowire MOSFETs Including Long/Short-Channel and Thin/Thick-Body Effects," (Invited Paper), Proc. of the 10th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2010), Shanghai, China, Nov. 2010, pp. 1725-1728.

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  7. X. Zhou, G. J. Zhu, S. H. Lin, Z. H. Chen, M. K. Srikanth, Y. F. Yan, R. Selvakumar, W. Chandra, J. B. Zhang, C. Q. Wei, Z. H. Wang, and P. Bathla, "Subcircuit Approach to Inventive Compact Modeling for CMOS Variability and Reliability," Proc. of the 12th International Symposium on Integrated Circuits, Devices & Systems (ISIC2009), Singapore, Dec. 2009, pp. 133-138.

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  9. G. J. Zhu, X. Zhou, Y. K. Chin, K. L. Pey, G. H. See, S. H. Lin, and J. B. Zhang, “Subcircuit Compact Model for Dopant-Segregated Schottky Silicon-Nanowire MOSFETs,” Proc. of the 2009 International Conference on Solid State Devices and Materials (SSDM2009), Miyagi, Japan, Oct. 2009, pp. 402-403.

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  11. X. Zhou, G. J. Zhu, G. H. See, J. B. Zhang, S. H. Lin, C. Q. Wei, Z. H. Chen, M. K. Srikanth, Y. F. Yan, R. Selvakumar, and W. Chandra, “Unified Compact Modeling for Bulk/SOI/FinFET/SiNW MOSFETs,” (Invited Paper), Proc. of the 2nd International Workshop on Electron Devices and Semiconductor Technology (IEDST2009), Mumbai, India, June 2009, Paper I8.

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  13. X. Zhou, G. J. Zhu, M. K. Srikanth, R. Selvakumar, Y. F. Yan, W. Chandra, J. B. Zhang, S. H. Lin, C. Q. Wei, and Z. H. Chen, "Compact Model Application to Statistical/Probabilistic Technology Variations," Proc. of the 12th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2009), Houston, TX, May 2009, pp. 612-615.

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  15. G. J. Zhu, X. Zhou, T. S. Lee, L. K. Ang, G. H. See, and S. H. Lin, "A Compact Model for Undoped Symmetric Double-Gate MOSFETs with Schottky-Barrier Source/Drain," Proc. of the 2008 European Solid-State Device Research Conference (ESSDERC2008), Edinburgh, UK, Sep. 15-19, 2008, pp. 182-185.

Related Presentations

  1. "Neutral Interface Traps for Negative Bias Temperature Instability," 2011 IEEE Reliability Physics Symposium (IRPS2011), Monterey, CA, Apr. 13, 2011.

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  3. "A Unified Compact Model for Emerging DG FinFETs and GAA Nanowire MOSFETs Including Long/Short-Channel and Thin/Thick-Body Effects," (Invited Paper), the 10th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2010), Shanghai, China, Nov. 2, 2010.

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  5. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk (IEEE EDS Distinguished Lecture Program), UC San Diego, June 25, 2010.

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  7. "Subcircuit Approach to Inventive Compact Modeling for CMOS Variability and Reliability," the 12th International Symposium on Integrated Circuits, Devices & Systems (ISIC2009), Singapore, Dec. 15, 2009.

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  9. "Unification of MOSFET Compact Models with the Unified Regional Modeling Approach," (Invited Talk), MOS-AK Workshop, Baltimore, MD, Dec. 9, 2009.

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  11. "Compact Model Application to Statistical/Probabilistic Technology Variations," Invited Talk, Indian Institute of Technology - Bombay, Mumbai, Nov. 20, 2009.

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  13. "Compact Model Application to Statistical/Probabilistic Technology Variations," Invited Talk, Technical University of Munich, Germany, Oct. 13, 2009.

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  15. "Compact Model Application to Statistical and Probabilistic Technology Variations," Invited Talk, Workshop on Sustainable Nanoelectronics and Information Technology, Rice Univ., Houston, TX, June 24, 2009.

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  17. "Unified Compact Modeling for Bulk/SOI/FinFET/SiNW MOSFETs," the 2nd International Workshop on Electron Devices and Semiconductor Technology (IEDST2009), Mumbai, India, June 2, 2009.

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  19. "Compact Model Application to Statistical/Probabilistic Technology Variations," the 12th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2009), Houston, TX, May 6, 2009.

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  21. "Unified Compact Modeling of Emerging Multiple-Gate MOSFETs," Invited Talk (IEEE EDS Distinguished Lecture Program), Sematech, Austin, TX, Aug. 7, 2008.

Related Theses

  1. Mr. Wang Zhihuan, "Numerical Characterization of Nanowire Transistors and Logic Gates with Parametric Variations for Probabilistic-CMOS," M.Sc. Dissertation.  (starting August 2009; finished January 2011).

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  3. Mr. Machavolu Kamakshi Srikanth, "Variability Study of Nanowire: A Compact Model Application," M.Sc. Dissertation.  (starting August 2008, finished July 2009).

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