Compact Model Application to Logic/Circuit Design of Futuristic Probabilistic-CMOS

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Compact Model Application to Logic/Circuit Design of Futuristic Probabilistic-CMOS

Executive Summary

As semiconductor technology continues to scale following Moore's Law, increased power will eventually limit further increase in speed and density.  To sustain technology scaling and prolong the promise the industry has benefited from scaling, one of the novel concepts has been proposed -- "probabilistic CMOS" (PCMOS) -- that exploits randomness in futuristic devices by taking advantage of probabilistic behaviors into chip designs.  By allowing uncertainties in certain parts of the functional blocks for trading off power savings, algorithms with probabilistic Boolean theories have demonstrated feasibility and promising potential for PCMOS in sustaining future technology scaling.

PCMOS approach to futuristic chip designs requires a paradigm shift in algorithms and methodologies, so do the device models and circuit simulators supporting such a new design.  Conventional and existing models/simulators obviously cannot fulfill such demands.  The innovative concepts in this project are two-folds: (1) a transistor compact model with link to physical noise modeling and process variations that is applicable as a building block in PCMOS design; and (2) a circuit simulator that bridges transistor and logic levels of abstraction so that the probabilistic behaviors captured at the device level can be propagated to the logic level within the PCMOS algorithms.

The first claim is a necessary condition for PCMOS design since its founding theory is based on probability.  Such randomness has to come from nature rather than being artificial.  Noise is nature's carpet that hides imperfections.  Another natural source of randomness comes from process fluctuations in fabrication.  These two are undesirables in conventional chip designs but are essential "resources" in PCMOS.  Although existing compact models to certain extent also include these features, they are not designed for use in PCMOS.  The proposed research is to develop such a model to capture noise/process-related randomness in a physical deterministic way (as required by the very nature of any compact model) and use it in a probabilistic way in PCMOS circuit/logic designs.  Without these specially developed transistor-level models it is impossible to do PCMOS designs.

The second claim is a sufficient condition for PCMOS design, even though without such a simulator conventional SPICE may still do the job if the "probabilistic" compact model can be deployed.  However, it will not be trivial without a circuit simulator that has dual representation (circuit/logic) and can handle probabilistic Boolean algorithms.  Although PCMOS is based on randomness, it is not meant to be totally "arbitrary" -- it is still required to designate parts of the logic circuits where certain probability of randomness can be tolerated (or to be "designed").  In this sense, it is also "deterministic" which requires a simulator that can designate a given block to be simulated with the desired randomness.

The two innovative ideas in the project are the key to realization of PCMOS designs of futuristic ICs.  Moreover, its impact goes beyond application to PCMOS alone, since nanoscale devices are already prone to suffer from intrinsic noise and inevitable process fluctuations that are to be avoided in "deterministic CMOS" (DCMOS).  In either domain of PCMOS or DCMOS for employing or avoiding nature randomness, respectively, a physical compact model capable of capturing randomness and propagating to circuit/gate level in either probabilistic or deterministic way will be a must in the foreseeable future.