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Workshop on Compact Modeling at the 9th International Conference on Modeling and Simulation of Microsystems |
Date
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May 9-11, 2006 | |
Venue | Hynes Convention Center
Boston, Massachusetts, USA |
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Synopsis | Compact Models
(CMs) for circuit simulation have been at the heart of CAD tools for circuit
design over the past decades, and are playing an ever increasingly important
role in the nanometer system-on-chip (SOC) era. As the mainstream
MOS technology is scaled into the nanometer regime, development of a truly
physical and predictive compact model for circuit simulation that covers
geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes
a major challenge.
Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation:
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Invited Speakers | Invited speakers from all over the
world are listed below:
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Workshop
Program |
WCM2006
Program has been posted at the following web:
There are 27 invited papers, which are categorized in the following topic areas: Bulk MOS intrinsic models
Chih-Tang Sah, University of Florida, US Matthias Bucher, Technical University of Crete, GR Carlos Galup-Montoro, Universidade Federal de Santa Catarina, BR Gennady Gildenblat, Pennsylvania State University, US John Hauser, North Carolina State University, US Jin He, Peking University, CN Bin Jie, University of Florida, US Mitiko Miura-Mattausch, Hiroshima University, JP Sivakumar Mudanai, Intel, US Michael Shur, Rensselaer Polytechnic Institute, US Xing Zhou, Nanyang Technological University, SG
Mohan Dunga, University of California at Berkeley, US Christian Enz, Swiss Center for Electronics and Microtechnology, CH Tor Fjeldly, Norwegian University of Science and Technology, NO Jerry Fossum, University of Florida, US Benjamín Iñíguez, Universitat Rovira i Virgili, ES Fabien Prégaldiny, InESS, FR Man Wong, Hong Kong University of Science and Technology, HK Yuan Taur, University of California at San Diego, US
Colin McAndrew, Freescale Semiconductor, US Josef Watts, IBM, US
Robert Dutton, Stanford University, US
Dirk Klaassen, Philips Research Laboratories, NE Ehrenfried Seebacher, Austriamicrosystems AG, AT
Juin Liou, University of Central Florida, US
Ramana Malladi, IBM, US Michael Schröter, University of Technology Dresden, DE |
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Poster Session | Poster
presentations in the scope of "compact models for circuit simulation" are
solicited. Please note that only posters submitted to WCM will be
considered. A 5-minute oral briefing
for each poster paper is planned.
See Nanotech website for instructions for authors: There are 35 contributed poster papers, which are listed below (speakers underlined).
C. McAndrew, Freescale Semiconductor, US G.H. See, S.B. Chiah, X. Zhou, K. Chandrasekaran, W. Shangguan, Z. Zhu, G.H. Lim, S.M. Pandey, M. Cheng, S. Chu, and L-C Hsia, Nanyang Technological University, SG P.D. da Silva, F.R. de Sousa, C.G. Montoro and M.C. Schneider, Federal University of Santa Catarina, BR V.C. Paim, C. Galup-Montoro and M.C. Schneider, Federal University of Santa Catarina, BR A.S. Roy and C.C. ENz, Swiss Federal Institute of Technology, Lausanne (EPFL), CH Y.Z. Xiong, G.Q. Lo, J.L. Shi, M.B. Yu, W.Y. Loh and D.L. Kwong, Institute of Microelectronics, SG R. Malladi, V. Borich, S.L. Sweeney, J. Rascoe, K.M. Newton, S. Venkatadri, J. Yang and S. Chen, IBM Systems and Technology, US M. Erturk, R. Anna, J.C. Lee, L.H. Pan, J.R. Jones, K.M. Newton, T. Xia and C.J. LaMothe, IBM Systems and Technology, US J.C. Lee, R.B. Anna, L.H. Pan and K.M. Newton, IBM Systems and Technology, US Y. Ma, M-C Jeng and Z. Liu, Cadence Design Systems, US Y. Ma, P. Chen, M-C Jeng and Z. Liu, Cadence Design Systems, US Y. Mahotin and S. Tirumala, Synopsys, US J. He, Z. Xing, G. Zhang and Y. Wang, Peking University, CN Z.M. Zhu, K. Chandrasekaran, X. Zhou, W. Shangguan, G.H. See, S.B. Chiah, S.C. Rustagi and N. Singh, Nanyang Technological University, SG M. Reyboz, O. Rozeau, T. Poiroux, P. Martin and J. Jomaah, CEA, FR T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki, S. O’uchi and H. Koike, National Institute of Advanced Industrial Science and Technology, JP O. Cobianu and M. Glesner, Darmstadt University of Technology, DE X. Loussier, D. Munteanu, J.L. Autran, S. Harrison and R. Cerutti, L2MP, FR O. Tintori, X. Loussier, D. Munteanu, J.L. Autran, A. Regnier and R. Bouchakour, L2MP, FR K. Goel, M. Saxena, M. Gupta and R.S. Gupta, University of Delhi South Campus, IN A. Kranti and G.A. Armstrong, Queen's University of Belfast, UK H. Abebe, E. Cumberbatch, H. Morris and S. Uno, San Jose State University, US A. Botula, S. Furkay, D.C. Sheridan, J.M. Johnson and M-H Na, IBM Corporation, US Q. Chen, Z-Y Wu, A.B. Icel, J-S Goo, S. Krishnan, C. Thuruthiyil, N. Subba, S. Suryagandh, J.X. An, T. Ly, M. Radwin, J. Yonemura and F. Assad, Advanced Micro Devices, US M.V. Dunga, X. Xi, A.M. Niknejad and C. Hu, University of California, Berkeley, US Z. Jin, Y-M Lee, J. Watts, A. Bonaccio, G. Schroer and N. Pai, IBM, US F.G. Anderson, R.M. Rassel and M.A. Lavoie, IBM Microelectronics, US B.C. Paul, S. Fujita, M. Okajima and T. Lee, Toshiba America Research, JP J. Chen, Agere Systems, US S. Nawal, V. Venkataraman and M.J. Kumar, Indian Institute of Technology, New Delhi, IN R.Q. Williams, D. Chidambarrao, J.H. McCullen, S. Narasimha, T.G. Mitchell and D. Onsongo, IBM Corporation, US H.G.A. Huizing, D. Tio Castro, J.C.J. Paasschens and M.H.R. Lankhorst, Philips, NL F. Guigues, F. Rudolff and E. Kussener, L2MP UMR 6137 CNRS - ISEN-Toulon, FR M.C. Schneider, C. Galup-Montoro, M.B. Machado and A.I.A. Cunha, Federal University of Santa Catarina, BR H-C Wu, S. Mijalkovic and J.N. Burghartz, Delft University of Technology, NL |
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Presentation
Slides |
(Click on
each
to download the PDF file. © Copyright
of the PDF files belongs to the respective contributors. Last update:
August 5.)
Download and save the entire ZIP file of presentation slides (27MB) Xing Zhou, Opening Remark |
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Invited | Chih-Tang
Sah, Carrier Generation and Recombination Currents At Interface Traps
In Long-Channel Surface-Potential-Based MOS Transistor Compact
Carlos Galup-Montoro, Symbolic Charge-based MOSFET Model Gennady Gildenblat, Theory and Modeling Techniques Used in PSP Model John Hauser, An MOS Model with an Improved Mobility Model Jin He, Benchmark Tests on Conventional Surface Potential Based Charge-Sheet Models and PUNSIM Development Bin Jie, Accuracy of Long-Channel Surface-Potential-Based MOS Transistor Compact Models Mitiko Miura-Mattausch, Advanced Compact MOSFET Model HiSIM2 Based Surface Potentials with a Minimum Number of Approximations Sivakumar Mudanai, Halo Doping: Physical Effects and Compact Modeling Michael Shur, Compact Iterative Field Effect Transistor Model Xing Zhou, Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling Mohan Dunga, BSIM4 and BSIM Multi-Gate Progress Christian Enz, A Charge-Based Compact Model of Double Gate MOSFET Tor Fjeldly, Precise 2D Compact Modeling of Nanoscale DG MOSFETs Based on Conformal Mapping Techniques Jerry Fossum, Recent Upgrades and Applications of UFDG Fabien Prégaldiny, An Explicit Quasi-static Charge-based Compact Model for Symmetric DG MOSFET Man Wong, On the Modeling of the Current-Voltage Characteristics of a Symmetrical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with an Undoped Body Colin McAndrew, Device Correlation: Modeling using Uncorrelated Parameters, Characterization Using Ratios and Differences Josef Watts, Modeling Small MOSFETs Using Ensemble Devices Yang Liu, Effects of Scaling on Modeling of Analog RF MOS Devices Dirk Klaassen, High-Voltage LDMOS Compact Modeling Ehrenfried Seebacher, Analog Compact Modeling for a 20-120V HV CMOS Technology Juin Liou, Compact Modeling of Spiral Inductors for RF Applications Field-Effect Transistors Ramana Malladi, Development and Design Kit Integration of a Scalable and Statistical High Current Model for Advanced SiGe HBTs Michael Schröter, Charge-storage Calculation for Si-based Bipolar Transistors from Device Simulation Matthias Bucher, Recent Advances in the EKV3.0 MOSFET Model |
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Posters | Colin
McAndrew, Improved Basic Symmetry Tests for MOSFET Models
Guan Huei See, Scalable MOSFET Short-channel Charge Model in All Regions Marcio Schneider, Compact Modeling of Nonlinearities in Submicron MOSFETs Marcio Schneider, Charge-Based Formulation of Thermal Noise in Short-Channel MOS Transistors A. S. Roy, On the Compact Modelling of Induced Gate Noise in the MOS Transistor Ramana Malladi, Two-Tone Distortion Modeling for SiGe HBTs Using the High-Current Model M. Erturk, BSIM Model for MOSFET Flicker Noise Statistics: Technology Scaling, Area, and Bias Dependence J.C. Lee, Investigation of Substrate Current Effects and Modeling of Substrate Resistance Network for RFCMOS Yutao Ma, NQS Effects in MOSFET's and its Implementation in Advanced Compact Models Yutao Ma, Capacitance Modeling for LDMOS Yuri Mahotin, TCAD-based Process Dependant HSPICE Model Parameter Extraction Jin He, A Carrier Based Analytic Model for Undoped Surrounding-Gate MOSFETs Karthik Chandrasekaran, Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach Marina Reyboz, Explicit Compact Model of Independent Double Gate MOSFET T. Nakagawa, Capacitance Model for Four-Terminal DG MOSFETs X. Loussier, Compact Model of Drain-Current in Double-Gate MOSFETs Including Carrier Quantization and Short-channel Effects O. Tintori, Performance Analysis of Double-Gate MOSFET-based Circuits Using a Compact Model Implemented in Eldo IC Analog Simulator G. Alastair Armstrong, Compact Model for Short Channel Effects in Source/Drain Engineered Nanoscale Double Gate (DG) SOI MOSFETs H. Abebe, Compact Models for Double Gate and Surrounding Gate MOSFETs A. Botula, SOI CMOS Compact Modeling Based on TCAD Device Simulations Qiang Chen, On Idlow with Emphasis on Speculative SPICE Modeling Mohan Dunga, Dynamic Behavior Model for High-K MOSFETs Zhenrong Jin, A Simple Yet Accurate Mismatch Model for Circuit simulation F. G. Anderson, Enhanced Junction Depletion Capacitance Modeling B. C. Paul, A Compact Model of Ballistic CNFET for Circuit Simulation Richard Williams, Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90nm SOI ULSI Technology F. Guigues, Static Analog Design Methodology Ana Cunha, Interrelations Between Threshold Voltage Definitions and Extraction Methods H.-C. Wu, A Unified Parameter Extraction Procedure for Scalable Bipolar Transistor Model Mextram |
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Websites for Proceedings | http://www.nsti.org/procs/Nanotech2006v3/7
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WCM-MSM2006
official websites |
http://www.nsti.org/Nanotech2006/WCM2006/ | |
WCM2005 website | View 2005 WCM program and presentation slides | |
WCM2004
website
|
View 2004 WCM program and presentation slides | |
WCM2003 website | View 2003 WCM program and presentation slides | |
WCM2002 website | View 2002 WCM program and presentation slides |
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(Updated: August 5, 2006) |