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Click here for the WCM2005 official website at NanoTech2005
Workshop on Compact Modeling at the 8th International Conference on Modeling and Simulation of Microsystems
Date
May 10-12, 2005
Venue Anaheim Marriott & Convention Center
Anaheim, California, USA
Synopsis Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era.  As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge.

Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together.  The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors.  For WCM-MSM2005, it is planned to have an Invited-Speaker Session, a Forum and an Evening Panel Discussion, as well as a contributed Poster Session.  Highlights of WCM2005 include a Keynote paper by Prof. Chih-Tang Sah and a special joint-authored review paper by invited key contributors presented at the Forum.  The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation:

  • Bulk MOS intrinsic models
  • SOI/double-gate/multiple-gate/floating-gate MOS models
  • Bipolar/HBT/SiGe/GaN/JFET models
  • RF/noise/scalable capacitance/NQS models
  • Statistical/predictive/process-based models
  • Interconnection/passive device models
  • Extrinsic/parasitic element models
  • Reliability/hot carrier/tunneling/ESD  models
  • Atomic-level/quantum-mechanical compact models
  • Numerical/TCAD/behavioral/table-based models
  • Model parameter extraction and optimization
  • Model-simulator interface and standardization
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Invited Speakers Invited speakers from all over the world are listed below:
  • Narain Arora, Cadence Design Systems, USA
  • Matthias Bucher, Technical University of Crete, Greece
  • Yuhua Cheng, Siliconlinx, USA
  • Jamal Deen, McMaster University, Canada
  • Robert Dutton, Stanford University, USA
  • Carlos Galup-Montoro, Universidade Federal de Santa Catarina, Brazil
  • Gennady Gildenblat, Pennsylvania State University, USA
  • Keith Green, Texas Instruments, USA
  • Chenming Hu, University of California at Berkeley, USA
  • Benjamín Iñíguez, Universitat Rovira i Virgili, Spain
  • Dirk Klaassen, Philips Research Laboratories, The Netherlands
  • Ronald van Langevelde, Philips Research Laboratories, The Netherlands
  • Luca Larcher, Università di Modena e Reggio Emilia, Italy
  • Shiuh-Wuu Lee, Intel, USA
  • Juin Liou, University of Central Florida, USA
  • Colin McAndrew, Freescale Semiconductor, USA
  • Mitiko Miura-Mattausch, Hiroshima University, Japan
  • Ali Niknejad, University of California at Berkeley, USA
  • Guofu Niu, Auburn University, USA
  • Adelmo Ortiz-Conde, Universidad Simón Bolívar, Venezuela
  • Rafael Rios, Intel, USA
  • Chih-Tang Sah, University of Florida, USA
  • Samar Saha, Silicon Storage Technology, USA
  • Michael Schröter, University of Technology Dresden, Germany
  • Yuan Taur, University of California at San Diego, USA
  • Josef Watts, IBM, USA
  • Xing Zhou, Nanyang Technological University, Singapore
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Keynote
  • Chih-Tang Sah, University of Florida, US

  • "A History of MOS Transistor Compact Modeling"
View/download paper
Workshop
Program
Workshop program has been posted on the Nanotech web:
http://www.nsti.org/Nanotech2005/program.html

There are 21 invited papers, which are categorized in the following topic areas:

Bulk MOS intrinsic models

  • Advances in Charge-Based Compact MOSFET Modelling

  • Matthias Bucher, Technical University of Crete, GR
  • Comparison of Surface Potential and Charge-based MOSFET Core Models

  • Carlos Galup-Montoro, Universidade Federal de Santa Catarina, BR
  • Introduction to PSP MOSFET Model

  • Gennady Gildenblat, Pennsylvania State University, US
  • Unified Regional Charge-based Versus Surface-potential-based Compact Modeling Approaches

  • Xing Zhou, Nanyang Technological University, SG
RF modeling
  • RF-MOSFET Model Parameter Extraction with HiSIM

  • Mitiko Miura-Mattausch, Hiroshima University, JP
  • Challenges in Compact Modeling for RF and Microwave Applications

  • Ali Niknejad, University of California at Berkeley, US
  • A Study of Figures of Merit for the High Frequency Behavior of MOSFETs in RF IC Applications

  • Yuhua Cheng, Siliconlinx, US
Double/multiple-gate MOS models
  • Compact Modeling of Multiple-gate SOI MOSFETs

  • Benjamín Iñíguez, Universitat Rovira i Virgili, ES
  • Analytic Solution for the Drain Current of Undoped Symmetric Dual-Gate MOSFET

  • Adelmo Ortiz-Conde, Universidad Simón Bolívar, VE
  • Physics-Based, Non-Charge-Sheet Compact Modeling of Double-Gate MOSFETs

  • Yuan Taur, University of California at San Diego, US
High-K
  • Mobility Extraction and Compact Modeling for FETs Using High-K Gate Materials

  • Robert Dutton, Stanford University, US
Noise modeling
  • The Effects of the Gate Tunneling Current on the High Frequency Noise Parameters of MOSFETs

  • Jamal Deen, McMaster University, CA
  • Correlated Noise Modeling and Simulation

  • Colin McAndrew, Freescale Semiconductor, US
Interconnect models
  • Modeling and Characterization of High Frequency Effects in ULSI Interconnects

  • Narain Arora, Cadence Design Systems, US
Modeling for design
  • Modeling for Pre-Silicon Design Verification

  • Shiuh-Wuu Lee, Intel, US
  • Modeling FET Variation Within a Chip as a Function of Circuit Design and Layout Choices

  • Josef Watts, IBM, US
High-voltage LDMOS models
  • Compact Modelling of High-Voltage LDMOS Devices

  • Dirk Klaassen, Philips Research Laboratories, NE
Bipolar/HBT models
  • Two-/Three-Dimensional GICCR for Si/SiGe Bipolar Transistors

  • Michael Schröter, University of Technology Dresden, DE
  • Physics and Modeling of Noise in SiGe HBT Devices and Circuits

  • Guofu Niu, Auburn University, US
JFET models
  • Compact Modeling of Four-Terminal Junction Field-Effect Transistors

  • Juin Liou, University of Central Florida, US
Floating-gate models
  • Statistical Simulations of Oxide Leakage Current in MOS Transistor and Floating Gate Memories

  • Luca Larcher, Università di Modena e Reggio Emilia, IT
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Forum A special 2-hour Forum is organized to focus on MOSFET Compact Model Utopia, with the topic on:
Surface-potential versus charge based approaches to MOSFET compact modeling.
A special joint-authored review paper is planned with invited key contributors in the field, edited by Josef Watts (IBM) and presented by Colin McAndrew (Freescale) on behalf of all the co-authors, followed by invited Forum presenters from representative model developers of surface-potential and charge-based approaches.  This Forum represents an important event and milestone for WCM in bringing people together in the CM field.
Forum chair Colin McAndrew, Freescale Semiconductor, USA
Joint paper co-authors "Advanced Compact Models for MOSFETs"
  • Josef Watts (editor), IBM, USA
  • Colin McAndrew (presenter), Freescale Semiconductor, USA
  • Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland
  • Carlos Galup-Montoro, Universidade Federal de Santa Catarina, Brazil
  • Gennady Gildenblat, Pennsylvania State University, USA
  • Chenming Hu, University of California at Berkeley, USA
  • Ronald van Langenvelde, Philips Research Laboratories, The Netherlands
  • Mitiko Miura-Mattausch, Hiroshima University, Japan
  • Rafael Rios, Intel, USA
  • Chih-Tang Sah, University of Florida, USA
View/download paper
Forum presenters
  • Colin McAndrew, Freescale Semiconductor, USA
  • Matthias Bucher, Technical University of Crete, Greece
  • Carlos Galup-Montoro, Universidade Federal de Santa Catarina, Brazil
  • Gennady Gildenblat, Pennsylvania State University, USA
  • Chenming Hu, University of California at Berkeley, USA
  • Ronald van Langevelde, Philips Research Laboratories, The Netherlands
  • Mitiko Miura-Mattausch, Hiroshima University, Japan
  • Rafael Rios, Intel, USA
  • Yuan Taur, University of California at San Diego, USA
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Evening Panel Discussion An evening Panel discussion is planned, continuing the debate on different modeling approaches in the Forum as well as on MOSFET Compact Model Development Utopia, with the question:
How to engage a diversified model developer community towards the same ultimate goal?

Some of the proposed questions include:

- Can a "best model" be built out of "best pieces" from various sources?
- How many MOSFET models do we need?
- What does it take to move a model from academia to industry?
- Do we need standard models or model standards?
Panel chair Narain Arora, Cadence Design Systems, USA
Moderator Josef Watts, IBM, USA
Panelist
  • Matthias Bucher, Technical University of Crete, Greece
  • Gennady Gildenblat, Pennsylvania State University, USA
  • Keith Green, Texas Instruments, USA
  • Chenming Hu, University of California at Berkeley, USA
  • Shiuh-Wuu Lee, Intel, USA
  • Mitiko Miura-Mattausch, Hiroshima University, Japan
  • Samar Saha, Silicon Storage Technology, USA
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Poster Session Poster presentations in the scope of "compact models for circuit simulation" are solicited.  A 10-minute oral briefing for each poster paper is planned.  Contributed poster papers are listed below.
  • Optimized Compact MOS Transistor Model from the Exact 4-component Theory

  • Bin B. Jie, University of Florida, US
  • All-Region MOS Model of Mismatch due to Random Dopant Placement

  • M. Schneider, Universidade Federal de Santa Catarina, BR
  • Analog Design Tool Based on the ACM Model

  • M. Schneider, Universidade Federal de Santa Catarina, BR
  • Extraction of MOSFET Effective Channel Length and Width Based on the Transconductance-to-Current Ratio

  • M. Schneider, Federal University of Bahia, BR
  • Unambiguous Extraction of Threshold Voltage Based on the Transconductance-to-Current Ratio

  • M. Schneider, Federal University of Bahia, BR
  • One-Iteration Parameter Extraction for Length/Width-Dependent Threshold Voltage and Unified Drain Current Model

  • Siau Ben Chiah, Nanyang Technological University, SG
  • Unified Regional Charge-Based MOSFET Model Calibration

  • Siau Ben Chiah, Nanyang Technological University, SG
  • RF Modeling for FDSOI MOSFET and Self Heating Effect on RF Parameter Extraction

  • Hui Wan, University of California at Berkeley, US
  • The Surface-Potential-Based Model HiSIM-SOI and Its Application to 1/f Noise in Fully-Depleted SOI-MOSFETs

  • N. Sadachika, Hiroshima University, JP
  • An A Priori Hysteresis Modeling Methodology for Improved Efficiency and Model Accuracy in Advanced PD SOI Technologies

  • Qiang Chen, AMD, US
  • SPICE Modeling of Multiple Correlated Electrical Effects of Dopant Fluctuations

  • Yoo-Mi Lee, IBM, US
  • A Compact Physical Model for Critical Quantum Mechanical Effects on MOSFET

  • Lihui Wang, Georgia Institute of Technology, US
  • A Compact model to Predict Quantized Sub-Band Energy Levels and Inversion Layer Centroid of MOSFET with Parabolic Potential Well Approximation

  • Jin He, University of California at Berkeley, US
  • A Compact Model for the Threshold Voltage of Silicon Nanowire MOS Transistors Including 2D-Quantum Confinement Effects

  • K. Nehari, Laboratoire Matériaux et Microélectronique de Provence, FR
  • Compact Modeling of Threshold Voltage in Double-Gate MOSFET Including Quantum Mechanical and Short Channel Effects

  • K. Nehari, Laboratory for Materials and Microelectronics of Provence, FR
  • Compact Model for Ultra-Short Channel Four-Terminal DG MOSFETs for Exploring Circuit Characteristics

  • T. Nakagawa, National Institute of Advanced Industrial Science and Technology, JP
  • Device Parameter Extraction from Fabricated Double-Gate MOSFETs

  • Toshiyuki Tsutsumi, National Institute of Advanced Industrial Science and Technology, JP
  • A Compact I-V Model for FinFETs Comprising Multi-Dimensional Electrostatics and Quantum Mechanical Effects

  • Zhiping Yu, Tsinghua University, CN
  • How to Design for Analog Yield Using Monte Carlo Mismatch SPICE Models

  • Philip Beow Yew Tan, Silterra Malaysia, MY
  • Modeling Snapback and Rise-time Effects in TLP Testing for ESD MOS Devices Using BSIM3 and VBIC Models

  • Yuanzhong Zhou, Fairchild Semiconductor, US
  • Airgap and Line Slope Modeling for Interconnect

  • F. Badrieh, Cypress Semiconductor, US
  • HiSIM-1.2: The Effective Gate Length Validation with the Capacitance Data

  • Yoshihisa Iino, Silvaco Japan, JP
  • An Optimization Method of Deep Submicron SOI Compact Model Parameter Extraction

  • Y. Mahotin, Synopsys, US
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Presentation
Slides
(Click on each  to download the PDF file.  © Copyright of the PDF files belongs to the respective contributors.  Last update: June 1, 2005.)
Download and save ...Download and save the entire ZIP file of presentation slides (27MB)

View SlidesXing Zhou, Openning Remark

Keynote View SlidesChih-Tang Sah, A History of MOS Transistor Compact ModelingView/download paper
Invited View SlidesMatthias Bucher, Advances in Charge-Based Compact MOSFET Modelling
View SlidesCarlos Galup-Montoro, Comparison of Surface Potential and Charge-based MOSFET Core Models
View SlidesGennady Gildenblat, Introduction to PSP MOSFET Model
View SlidesXing Zhou, Unified Regional Charge-based Versus Surface-potential-based Compact Modeling Approaches
View SlidesJamal Deen, The Effects of the Gate Tunneling Current on the High Frequency Noise Parameters of MOSFETs
View SlidesColin McAndrew, Correlated Noise Modeling and Simulation
View SlidesHans Juergen Mattausch, RF-MOSFET Model Parameter Extraction with HiSIM
View SlidesAli Niknejad, Challenges in Compact Modeling for RF and Microwave Applications
View SlidesYuhua Cheng, A Study of Figures of Merit for the High Frequency Behavior of MOSFETs in RF IC Applications
View SlidesBenjamín Iñíguez, Compact Modeling of Multiple-gate SOI MOSFETs
View SlidesAdelmo Ortiz-Conde, Analytic Solution for the Drain Current of Undoped Symmetric Dual-Gate MOSFET
View SlidesNarain Arora, Modeling and Characterization of High Frequency Effects in ULSI Interconnects
View SlidesJosef Watts, Modeling FET Variation Within a Chip as a Function of Circuit Design and Layout Choices
View SlidesDirk Klaassen, Compact Modelling of High-Voltage LDMOS Devices
View SlidesMichael Schröter, Two-/Three-Dimensional GICCR for Si/SiGe Bipolar Transistors
View SlidesGuofu Niu, Physics and Modeling of Noise in SiGe HBT Devices and Circuits
View SlidesJuin Liou, Compact Modeling of Four-Terminal Junction Field-Effect Transistors
View SlidesLuca Larcher, Statistical Simulations of Oxide Leakage Current in MOS Transistor and Floating Gate Memories
Forum View SlidesColin McAndrew, "Surface-potential versus charge based approaches to MOSFET compact modeling"
View SlidesJoint Paper, Advanced Compact Models for MOSFETsView/download paper
View SlidesMatthias Bucher, "Inversion charge" vs. "surface potential" model
View SlidesCarlos Galup-Montoro, Surface Potential vs. Charge-based MOSFET Models
View SlidesGennady Gildenblat, Surface Potential or Inversion Charge?
View SlidesChenming Hu, Tale of Two Models
View SlidesRonald van Langevelde, Surface-potential versus charge based approaches to MOSFET compact modeling
View SlidesHans Juergen Mattausch (Mitiko Miura-Mattausch), Surface-Potential-Based Modeling: Indispensable for Compact Models
View SlidesRafael Rios, How Critical is the Core Model Choice?
View SlidesYuan Taur, Surface potential vs. Inversion charge based approaches to MOSFET compact modeling
Panel View SlidesNarain Arora, "How to engage a diversified model developer community towards the same ultimate goal?"
View SlidesMatthias Bucher, "Model diversity" vs. "model standard"
View SlidesGennady Gildenblat, Engaging Modeling Community
View SlidesKeith Green, WCM Panel Questions on SPICE MOSFET Model Standards
View SlidesChenming Hu, Thoughts on Compact Model
View SlidesShiuh-Wuu Lee, How to engage a diversified model developer community towards the same ultimate goal?
View SlidesHans Juergen Mattausch (Mitiko Miura-Mattausch), Model standardization is good for focusing the community. On a sustained evolution of improvements for the future
View SlidesSamar Saha, How to engage a diversified model developer community towards the same ultimate goal?
Posters View SlidesBin B. Jie, Optimized Compact MOS Transistor Model from the Exact 4-component Theory
View SlidesMarcio Schneider, All-Region MOS Model of Mismatch due to Random Dopant Placement
View SlidesMarcio Schneider, Analog Design Tool Based on the ACM Model
View SlidesMarcio Schneider, Extraction of MOSFET Effective Channel Length and Width Based on the Transconductance-to-Current Ratio
View SlidesMarcio Schneider, Unambiguous Extraction of Threshold Voltage Based on the Transconductance-to-Current Ratio
View SlidesSiau Ben Chiah, One-Iteration Parameter Extraction for Length/Width-Dependent Threshold Voltage and Unified Drain Current Model
View SlidesSiau Ben Chiah, Unified Regional Charge-Based MOSFET Model Calibration
View SlidesHui Wan, RF Modeling for FDSOI MOSFET and Self Heating Effect on RF Parameter Extraction
View SlidesQiang Chen, An A Priori Hysteresis Modeling Methodology for Improved Efficiency and Model Accuracy in Advanced PD SOI Technologies
View SlidesK. Nehari, A Compact Model for the Threshold Voltage of Silicon Nanowire MOS Transistors Including 2D-Quantum Confinement Effects
View SlidesK. Nehari, Compact Modeling of Threshold Voltage in Double-Gate MOSFET Including Quantum Mechanical and Short Channel Effects
View SlidesT. Nakagawa, Compact Model for Ultra-Short Channel Four-Terminal DG MOSFETs for Exploring Circuit Characteristics
View SlidesJin He (Hui Wan), A Compact model to Predict Quantized Sub-Band Energy Levels and Inversion Layer Centroid of MOSFET with Parabolic Potential Well Approximation
View SlidesToshiyuki Tsutsumi, Device Parameter Extraction from Fabricated Double-Gate MOSFETs
View SlidesZhiping Yu, A Compact I-V Model for FinFETs Comprising Multi-Dimensional Electrostatics and Quantum Mechanical Effects
View SlidesPhilip Beow Yew Tan, How to Design for Analog Yield Using Monte Carlo Mismatch SPICE Models
View SlidesYuanzhong Zhou, Modeling Snapback and Rise-time Effects in TLP Testing for ESD MOS Devices Using BSIM3 and VBIC Models
View SlidesF. Badrieh, Airgap and Line Slope Modeling for Interconnect
View SlidesYoshihisa Iino, HiSIM-1.2: The Effective Gate Length Validation with the Capacitance Data
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Websites for Proceedings http://www.nsti.org/procs/Nanotech2005WCM
(Keynote, Invited, Poster)

Nanotech2005-WCM Preface
WCM-MSM2005
official websites
http://www.nsti.org/Nanotech2005/WCM2005/
WCM2004 website View 2004 WCM program and presentation slides
WCM2003 website View 2003 WCM program and presentation slides
WCM2002 website View 2002 WCM program and presentation slides

Download PDFClick to download the program (PDF) (Updated: June 1, 2005)
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