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Workshop on Compact Modeling (WCM-MSM2003)

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WCM MSM2003	Workshop on Compact Modeling at the 6th International Conference on Modeling and Simulation of Microsystems
Date	February 25-27, 2003
Venue	Grand Hyatt San Francisco San Francisco, California, USA
Synopsis	Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the very-deep-submicron/system-on-chip (VDSM/SOC) era. As the mainstream MOS technology is scaled into the VDSM regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge. Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. For WCM-MSM2003, it is planned to have an Invited-Speaker Session, an Evening Forum on "Model development - industry requirement dialogue", contributed Poster Session as well as Tutorial Session. The topics are extended to the following areas, within the main theme - compact models for circuit simulation: Bulk MOS intrinsic models SOI/double-gate MOS models Bipolar/HBT/SiGe models RF/noise/scalable capacitance/NQS models Statistical/predictive/process-based models Interconnection/passive device models Extrinsic/parasitic element models Reliability/hot carrier/tunneling models Atomic-level/quantum-mechanical compact models Numerical/TCAD/behavioral/table-based models Model parameter extraction and optimization Model-simulator interface and standardization	top
Invited Speakers	Invited speakers as well as panelists for the WCM Forum from all over the world (10 countries) are listed below (speakers underlined): Narain Arora, Cadence Design Systems, USA Peter Bendix, LSI Logic, USA Mansun Chan, Hong Kong University of Science and Technology, Hong Kong Robert Dutton, Stanford University, USA Jerry Fossum, University of Florida, USA Carlos Galup-Montoro and Marcio Schneider, Universidade Federal de Santa Catarina, Brazil Gennady Gildenblat and Xin Gu, Pennsylvania State University, USA Thomas Gneiting, Advanced Modeling Solutions, Germany Hermann Gummel, Averill Bell, and Kumud Singhal, Agere Systems, USA Chenming Hu, Ali Niknejad, and Xuemei Xi, University of California at Berkeley, USA; (also with Taiwan Semiconductor Manufacturing Company) Dirk Klaassen and Jeroen Paasschens, Philips Research Laboratories, The Netherlands Shiuh-Wuu Lee, Intel, USA Colin McAndrew, Wladyslaw Grabinski**, and Laurent Lemaitre**, Motorola, USA, *Switzerland Marek Mierzwinski, Tiburon Design Automation, USA Mitiko Miura-Mattausch, Hiroshima University, Japan Andrea Pacelli, State University of New York at Stony Brook, USA Mahesh Patil, Indian Institute of Technology - Bombay, India Greg Rollins, Mentor Graphics, USA Michael Schroter, University of Technology Dresden, Germany Hyungcheol Shin, Korea Advanced Institute of Science and Technology, Korea Bogdan Tudor, Synopsys, USA Eric Vittoz, Christian Enz, and Francois Krummenacher*, Swiss Center for Electronics and Microtechnology, EPFL, Switzerland Simon Wong, Niranjan Talwalkar, and Patrick Yue, Stanford University, USA Cary Yang and Sang-Pil Sim, Santa Clara University, USA Xing Zhou, Nanyang Technological University, Singapore	top
Workshop Program	There are 22 invited papers, which are categorized in the following topic areas (speakers underlined): *Compact modeling and design: Implications of Gate Tunneling and Quantum Effects in the Gate-Channel Stack Robert Dutton and Chang-Hoon Choi, Stanford University, USA* A Basic Property of MOS Transistors and its Circuit Implications Eric Vittoz, Christian Enz, and Francois Krummenacher, Swiss Center for Electronics and Microtechnology, EPFL, Switzerland *Bulk MOS intrinsic models: USIM Design Considerations Averill Bell, Kumud Singhal, and Hermann Gummel, Agere Systems, USA* Theory, Development and Applications of the Advanced Compact MOSFET (ACM) Model Carlos Galup-Montoro, M. C. Schneider, A. I. A. Cunha, and O. C. Gouveia-Filho*, Universidade Federal de Santa Catarina, Escola Politécnica/UFBA - Salvador, *CIEL/UFPR - Curitiba, Brazil HiSIM: Accurate Charge Modeling Important for RF Era Mitiko Miura-Mattausch, D. Navarro, H. Ueno, H. J. Mattausch, K. Morikawa, S. Itoh, A. Kobayashi, and H. Masuda, Hiroshima University, Semiconductor Technology Academic Research Center, Japan* An Advanced Surface-Potential-Plus MOSFET Model Jin He, Xuemei Xi, Mansun Chan, Ali Niknejad, and Chenming Hu, University of California at Berkeley, USA, Hong Kong University of Science and Technology, Hong Kong A Technology-Based Compact Model for Predictive Deep-Submicron MOSFET Modeling and Characterization Xing Zhou, Siau Ben Chiah, and Khee Yong Lim, Nanyang Technological University, Chartered Semiconductor Manufacturing, Singapore *SOI/double-gate MOS models: A Framework for Generic Physics Based Double-Gate MOSFET Modeling Mansun Chan, Yuan Taur, Chung Hsun Lin, Jin He, Ali Niknejad, and Chenming Hu, Hong Kong University of Science and Technology, Hong Kong, University of California at San Diego, University of California at Berkeley, USA A Physics-Based Compact Model for Nano-Scale DG and FD/SOI MOSFETs Jerry Fossum, Lixin Ge, and Meng-Hsueh Chiang, University of Florida, USA* *Bipolar models: BJT Modeling with VBIC, Basics and V1.3 Updates Colin McAndrew, Motorola, USA* Compact Bipolar Transistor Modeling - Issues and Possible Solutions Michael Schroter, University of Technology Dresden, Germany *RF/noise models: Noise Modelling with MOS Model 11 for RF-CMOS Applications A. J. Scholten, L. F. Tiemeijer, R. van Langevelde, R. J. Havens, A. T. A. Zegers-van Duijnhoven, V. C. Venezia, and Dirk Klaassen, Philips Research Laboratories, The Netherlands* Physical Modeling of Substrate Resistance in RF MOSFETs Hyungcheol Shin, Jeonghu Han, and Minkyu Je, Korea Advanced Institute of Science and Technology, Korea *Interconnection/passive device models: Characterization and Modeling of Copper Interconnects for VLSI Design Narain Arora, Cadence Design Systems, USA* Compact Modeling for RF and Microwave Integrated Circuits Ali Niknejad, Mansun Chan, Chenming Hu, Xuemei Xi, Jin He, Pin Su, Yu Cao, Hui Wan, Mohan Dunga, Chinh Doan, Sohrab Emami, and Chung-Hsun Lin, University of California at Berkeley, USA, Hong Kong University of Science and Technology, Hong Kong Vector-Potential Equivalent Circuit for Efficient Modeling of Interconnect Inductance Andrea Pacelli, State University of New York at Stony Brook, USA Unified RLC Model for On-chip Interconnects Sang-Pil Sim and Cary Yang, Santa Clara University, USA Compact Modeling of High Frequency Phenomena for On-chip Spiral Inductors Niranjan Talwalkar, Patrick Yue, and Simon Wong, Stanford University, USA *Extrinsic/parasitic element models: Surface-Potential-Based Extrinsic MOSFET Model Xin Gu, Gennady Gildenblat,Glen Workman, and Shye Shapira, Pennsylvania State University, Motorola, *Agere Systems, USA *Model parameter extraction and optimization* A Unified Environment for the Modeling of Ultra Deep Submicron MOS Transistors Thomas Gneiting, Advanced Modeling Solutions, Germany *Model-simulator interface and standardization* Standardization of Compact Device Modeling in High Level Description Language Laurent Lemaitre, Colin McAndrew, and Wladyslaw Grabinski, Motorola, Switzerland, Motorola, USA Changing the Paradigm for Compact Model Integration in Circuit Simulators Using Verilog-A Marek Mierzwinski and Robert Dutton, Tiburon Design Automation, Stanford University, USA	top
Forum and Evening Panel	Forum on *Model development - industry requirement dialogue* Continued from the first successful Workshop on Compact Modeling (WCM-MSM2002) in San Juan, April 2002, this second Workshop (WCM-MSM2003) encompasses a broader range of topics, from intrinsic bulk MOS to bipolar and SOI/double-gate, as well as RF/interconnect/extrinsic/passive-element models, covering important issues on design considerations, parameter extraction, and simulator interface. To complement the invited technical presentations by experts from both academia and industry, a Forum on "model development - industry requirement dialogue" is organized, in which we are going to hear experts' views on the general topic: The Role of Compact Model in the Fab and Fabless Business An Evening Panel discussion will be followed by a panel of experts from major representative academic (Stanford, UC Berkeley), chip industry (Intel, LSI Logic, Philips), and EDA vendors (Cadence, Mentor Graphics, Synopsys). The Panel will discuss important topics that are in line with the theme of this Workshop: - Key to bridging compact-model development to designers and simulator vendors - Current needs and priorities in compact-model development - Intrinsic model with respect to extrinsic, parasitic, passive, and interconnect models - Model interface to simulators, extractors, and users We are expected to hear "spirited difference of opinions" on how to define, develop, and deploy a good compact model that is central to the mutual benefit of the entire chip design, modeling, and manufacturing communities.
Moderator	Narain Arora, Cadence Design Systems, USA
Panelists	Peter Bendix, LSI Logic, USA Robert Dutton, Stanford University, USA Dirk Klaassen, Philips Research Laboratories, The Netherlands Shiuh-Wuu Lee, Intel, USA Ali Niknejad, University of California at Berkeley, USA Greg Rollins, Mentor Graphics, USA Bogdan Tudor, Synopsys, USA	top
Poster Session	Poster presentations in the scope of "compact models for circuit simulation" are solicited. A 5-minute oral briefing for each poster paper is planned before the poster presentation session. Contributed poster papers are listed below (presenters underlined): A Physics-Based Analytical Surface Potential and Capacitance Model of MOSFET's Operation from the Accumulation to Depletion Region Jin He, Xuemei Xi, Mansun Chan, and Chenming Hu, University of California at Berkeley, USA Modeling of Direct Tunneling Current in Multi-Layer Gate Stacks Mohan V. Dunga, Xuemei Xi, Jin He, I. Polishchuk, Qiang Lu, Mansun Chan, Ali Niknejad, and Chenming Hu, University of California at Berkeley, USA Substrate Current in Surface-Potential-Based Compact MOSFET Models X. Gu and G. Gildenblat, Pennsylvania State University, USA Application of Genetic Algorithm to Compact MOSFET Model Parameter Extraction X. Cai, H. Wang, X. Gu, and G. Gildenblat, Pennsylvania State University, USA A Surface-Potential-Based Compact Model of NMOSFET Gate Tunneling Current X. Gu, H. Wang, G. Gildenblat, G. Workman, S. Veeraraghavan, S. Shapira, and K. Stiles, Pennsylvania State University, Motorola, *Agere Systems, USA Gate Current Partitioning Scheme for Circuit Simulation Q. Ngo, D. Navarro, T. Mizoguchi, S. Hosakawa, H. Ueno, M. Miura-Mattausch, and C. Y. Yang, Santa Clara University, USA, Hirohsima, Japan Double-Gate CMOS Evaluation for 45nm Technology Node Meng-Hsueh Chiang, Judy X. An, Zoran Krivokapic, and Bin Yu, Advanced Micro Devices, USA Primary Consideration on Compact Modeling of DG MOSFETs with Four-Terminal Operation Mode T. Nakagawa, T. Sekigawa, T. Tsutsumi, E. Suzuki, and H. Koike, National Institute of Advancet Industrial Science and Technology, Japan A Compact Model Methodology for Device Design Uncertainty Richard Williams, Josef Watts, Myung-hee Na, and Kerry Bernstein, IBM, USA Unified Length-/Width-Dependent Threshold Voltage Model with Reverse Short-Channel and Inverse Narrow-Width Effects Siau Ben Chiah, Xing Zhou, and Khee Yong Lim, Nanyang Technological University, Chartered Semiconductor Manufacturing, Singapore Unified Length-/Width-Dependent Drain Current Model for Deep-Submicron MOSFETs Siau Ben Chiah, Xing Zhou, and Khee Yong Lim, Nanyang Technological University, Chartered Semiconductor Manufacturing, Singapore An Interactive Website as a Tool for CAD of Power Circuits Bartlomiej Swiercz, Lukasz Starzak, Mariusz Zubert, and Andrzej Napieralski, Technical University of Lodz, Poland Multidimensional Model-Based Parameter Estimation Method for Compact Modeling of High-Speed Interconnects FET Tom Dhaene, University of Antwerp, Belgium An Automatic Macro Program Developed for Characterization, Parameter Extraction and Statistic Analysis of Spiral Inductors D. Y. Chiu, G. W. Huang, and K. M. Chen, National Nano Device Laboratories, Taiwan	top
Tutorial Session	Two tutorials are offered as listed below (speakers underlined): Modelling of Si and SiGe Bipolar Transistors with the Compact Model Mextram 504 Jeroen Paasschens and R. van der Toorn, Philips Research Laboratories, The Netherlands The Look-Up Table Approach and its Implementation in a Circuit Simulator Mahesh Patil, Indian Institute of Technology - Bombay, India	top
Presentation Slides	click here	top
Websites for Proceedings	http://www.nsti.org/procs/Nanotech2003v2/7 (Vol. 2, Chapter 7: Compact Modeling)
WCM-MSM2003 official websites	http://www.cr.org/MSM2003/WCM.html http://www.nanotech2003.com/WCM2003.html http://www.nsti.org/WCM2003.html

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