IEEE/EDS - VLSI Technology & Circuits

VLSI Technology and Circuits Technical Committee

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2001 IEDM Emerging Technologies Session

IEDM advance program	The 2001 IEDM Evening Panel Discussion *"Interconnecting Devices for the Terabit Era: Myths, Rumors, and Heresies"*
Organizer	IEEE Electron Devices Society Technical Committee on VLSI Technology and Circuits
Venue	Tuesday, December 4, 8:00 p.m. International Ballroom Center
Moderator	Jim Hutchby, SRC
Panel	Frank Chang, UCLA Karl Ebeling, Infineon Sadik Esener, UCSD Bob Markunas, Ziptronix Jim Meindl, Georgia Institute of Technology Shinichi Ogawa, SELETE Tom Theis, IBM Ian Young, Intel
Synopsis	Much has been said and written about the looming (arguably, current) problem of global interconnect (intra- and inter-chip), particularly related to intra-chip global clock/signal distribution. Views range from having to replace current Cu/Low-k global interconnect technology with an alternate solution by the 65-nm node in 2007, to the notion that this "incrementally worsening" problem can be managed via new systems architectures and Cu/Low-k global interconnect modifications. Eventually, however, accelerating clock frequencies (10’s of GHz) will drive Cu/Low-k global interconnects to their performance limit. Alternate solutions for global interconnect include optical and RF interconnects, and a variety of heterogeneous and monolithic 3D integration approaches. In this "interconnect soup" of controversial problem definition and myriad technological approaches, the following questions will be addressed by the panel: Is the "Global Interconnect Problem" a "Red Brick Wall" show stopper, or is it a soft limit that eventually will require alternate solutions? What are the issues defining the limits of Cu/Low-k from systems and microprocessor points of view? Is optical interconnect a viable technology approach for inter-chip applications? Will it ever be useful for intra-chip applications? Will RF interconnect provide a sufficient number of channels within an achievable bandwidth to be useful? Will 3D integration have significant impact on the global interconnect issue? What about the power dissipation and thermal management issues?