Motivation
Field Programmable Gate Arrays (FPGAs) are increasingly being adopted in embedded systems due to their ability to meet the technological and market uncertainties. Modern FPGA architectures incorporate a multitude of Intellectual Property cores that include soft and hard processors. The additional processing options that are available on FPGAs have increased the complexity of design space explorations, which have become unmanageable in traditional design methodologies especially for large applications. System-level design methodologies are expected to play a central role in the design success of current and future embedded products.
One of the key tasks in modern system-level design is to automatically generate/recommend suitable hardware-software components that meet the conflicting design constraints (cost, performance, power, time) in embedded systems. In order to identify suitable candidates for hardware realization, it is necessary to predict the quantitative outcome of mapping the application portions to hardware.
While high-level estimation has been employed in most of the commercial Application Specific Integrated Circuit (ASIC) based Electronic Design Automation (EDA) tools, accurate high level estimation of FPGA-based implementation remains a challenging research area. Till date, the most widely used FPGA-based design tools do not incorporate high-level estimation. The ability to achieve good estimation results for FPGA-based architectures is mainly hampered by the difficulty in predicting: 1) the effects of logic synthesis in FPGA tools for mapping the application code to the fine-grained programmable logic blocks, and 2) the post place and route interconnect delay. Existing works often lead to unreliable results as they do not consider the combined effects of logic synthesis and physical implementation during high-level estimation.
Research Objective
This research aims to develop a design exploration framework that can rapidly generate custom co-processor structures for FPGAs from C functions. In particular, the design exploration framework must incorporate efficient high-level area-time estimation that can accurately predict the quantitative outcome of mapping the application portions to FPGA without undergoing time-consuming RTL synthesis and implementation.
CRATE Framework
The CRATE framework relies on the Trimaran compiler infrastructure for its advanced scheduling schemes to expose the inherent parallelism in C-based algorithms. We have employed a co-processor template to assist in the estimation of the hardware data and control-path. The original Very Long Instruction Word (VLIW) machine model in Trimaran was modified to incorporate heterogeneous Functional Units (FUs) that will be bounded to the co-processor template.
The proposed data-path estimation technique relies on a hybrid approach, which uses bit-width sensitive estimation models that are based on pre-characterized parameters for area-time estimation of the FUs. In addition, the proposed delay estimation takes into account the post implementation interconnect delay by performing a simplified floor-planning procedure to predict the placement of the FUs on FPGA. A RTL code generator has been developed to automatically generate synthesizable RTL codes for a given C code segment.
