Motivation
Future embedded systems will require a higher degree of customization to manage the growing complexity of the applications. At the same time, they must continue to facilitate a high degree of flexibility to meet the shrinking Time-to-Market (TTM) window. There exists an urgent need to develop techniques that focus on increasing the design productivity of highly customized embedded systems, in order to improve product life cycles, and reduce TTM pressure and Non-Recurring Engineering (NRE) costs.
Computing platforms such as Reconfigurable Instruction Set Processors (RISPs) provide a promising solution to realize a balanced trade-off between flexibility and customization.
Research Objective
The main aim of this research work is to develop novel techniques and design methodologies for automatically generating efficient custom instructions that are capable of optimizing the utilization of RISPs. In particular, the proposed methods must incorporate architecture-aware strategies to generate area-time efficient custom instructions without the need to undergo time consuming hardware design iterations.
ARCTIC Framework
The Architecture AwaRe CusTom InstruCtions (ARCTIC) framework incorporates a number of novel techniques to realize area-time efficient custom instructions on RISPs. ARCTIC incorporates the following:
- Graph covering strategy for rapid selection of custom instructions.
- Cluster generation technique to estimate critical path delays and area utilization of custom instructions on Look-Up Table (LUT) based FPGAs.
- Design exploration framework that can rapidly identify a reduced set of profitable custom instructions without the need for actual hardware synthesis.
- Novel cluster merging strategy that takes into account the architectural constraints of the FPGA device in order to realize custom instructions with low area-delay product.
- Hierarchical loop partitioning strategy that reduces the complexity of the search space for determining the runtime custom instruction configurations in area constrained RISPs.
- Scheme for managing the runtime reconfiguration of custom instructions on a partially reconfigurable architecture.
