Session 30: Modeling and Simulation – Noise and Fluctuations
Wednesday, December 9, 9:00 a.m.
Key Ballroom 5

Co-Chairs: Paolo Fantini, Numonyx
Klaus von Arnim, Infineon Technologies

9:00 a.m.
Introduction

9:05 a.m.
30.1  Compact Model for Layout Dependent Variability (Invited), H. Aikawa, T. Sanuki, A. Sakata, E. Morifuji, H. Yoshimura, T. Asami, H. Otani, H. Oyamatsu, Toshiba Corporation Semiconductor

We have established a compact model which deals with MOSFET characteristic variations arising from complicated design layouts used in 45 nm CMOS technology node. By taking interactions between basic layout dependences, the model has acquired high applicability and predictability, which is verified by direct measurement of standard cells.

9:30 a.m.
30.2  Statistical Enhancement of Combined Simulations of RDD and LER Variability: What can Simulation of a 105 Sample Teach Us?, D. Reid, C. Millar, G. Roy, S. Roy, A. Asenov, University of Glasgow

Analysis of 100,000 simulations of combined RDD and LER variability has shown that the distribution of Vt matches the distribution obtained by mathematically combining the individual distributions. Methods for the statistical enhancement of RDD and LER simulations are presented and the accuracy of the methods is examined.

9:55 a.m.
30.3  Design Space and Scalability Exploration of 1T-1STT MTJ Memory Arrays in the Presence of Variability and Disturbances, A. Raychowdhury, D. Somasekhar, T. Karnik, V. De, Intel Corporation

This paper presents modeling and analysis of 1T-1MTJ STTRAM memory arrays under process variation and thermal disturbances. Bounds on the magnetic material design space for aggressive embedded applications have been shown. Impact of relaxed timing/area and the effect of scaling for 1T-1MTJ bitcells have been evaluated.

10:20 a.m.
30.4  Impact of Interface States on MOS Transistor Mismatch, P. Andricciola, H.P. Tuinhout, B. De Vries, N.A.H. Wils, A.J. Scholten, D.B.M. Klaassen, NXP Semiconductor

Statistical device simulations show that interface states fluctuating in terms of density, position and energy, have an enormous impact on mismatch fluctuations in sub-threshold. Through a new analysis method, based on mismatch signature and PCA, it is demonstrated that interface states should not be neglected for modern MOSFET mismatch modeling.

10:45 a.m.
30.5  Statistical Model for MOSFET Low-Frequency Noise under Cyclo-Stationary Conditions, R. da Silva, G. Wirth, P. Srinivasan*, J. Krick*, R. Brederlow*, UFRGS, *Texas Instruments

A statistical model for the low-frequency noise behavior of MOSFETs under cyclo-stationary excitation is presented. The model is based on discrete device physics quantities, which are shown to cause statistical variability in LF noise behavior. Good agreement between experimental data, Monte Carlo simulations and model is demonstrated.

11:10 a.m.
30.6  Compact Modeling of Flicker Noise Variability in Small Area MOSFETs, T.H. Morshed, M.V. Dunga, J. Zhang, D.D. Lu, A.M. Niknejad, C. Hu, University of California, Berkeley

A statistical compact model of flicker noise in scaled MOSFETs is presented, providing device size dependent noise mean and standard deviation. The model is verified with Monte Carlo simulation and experimental data. Our discovery that flicker noise exhibits log normal distribution is utilized to construct a compact model that allows designers to specify the sizes and desired % yields of critical devices when performing SPICE simulation of circuit performance.

11:35 a.m.
30.7  Distributed-Poole-Frenkel Modeling of Anomalous Resistance Scaling and Fluctuations in Phase-Change Memory (PCM) Devices, D. Fugazza, D. Ielmini, S. Lavizzari, A.L. Lacaita, Politecnico di Milano

A new distributed Poole-Frenkel conduction model for the active chalcogenide material in phase change memory is presented, accounting for anomalous resistance scaling and current fluctuations. Calculation results agree with experimental data and allow for scaling projections at nodes F = 45 - 8 nm for resistance window and signal-to-noise ratio.