Session 7: Modeling and Simulation - Compact Modeling
Monday, December 11, 1:30 p.m.
Continental Ballroom 6

Co-Chairs: Kuntal Joardar, Texas Instruments
Mitiko Miura-Mattausch, Hiroshima University

1:35 p.m.
7.1  PSP-based Compact FinFET Model Describing DC and RF Measurements, G.D.J. Smit, A.J. Scholten, N. Serra, R.M.T. Pijper, R. van Langevelde, A. Mercha*, G. Gildenblat**, D.B.M. Klaassen, Philips Research Laboratories, Eindhoven, The Netherlands, *IMEC Leuven, Belgium, **Arizona State University, AZ

We present a new, PSP-based compact model for symmetric 3-terminal FinFETs with thin undoped or lightly doped body, which is suitable for digital, analog, and RF circuit simulation. The model is surface potential based and is demonstrated to accurately describe both TCAD data and measured FinFET currents, conductances, and capacitances.

2:00 p.m.
7.2  A New Surface Potential Based Poly-Si TFT Model for Circuit Simulation, H. Tsuji, T. Kuzuoka, Y. Kishida, Y. Shimizu, M. Kirihara, Y. Kamakura, M. Morifuji, Y. Shimizu*, S. Miyano*, and K. Taniguchi, Osaka University, Osaka, Japan, *Advanced LCD Technologies Development Center Co., Ltd, Yokohama, Japan

A surface potential based poly-Si TFT model for circuit simulation was developed with accounting for the influence of trap states. The model describes the drain current in the all regions of operation by using the unified equation. Calculations with our drain current model are in good agreements with measured data.

2:25 p.m.
7.3  Surface Potential Based Poly-Si Thin-Film Transistor Model for SPICE, H. Ikeda, Sony Corporation, Kanagawa, Japan

Surface potential based poly-Si TFT model is proposed. Drain current model includes mobility modulations, hot carrier effect, GIDL, trap dependent generation. Capacitance model is based on physically partitioned charges. Primitive NQS model is also incorporated. This model covers various types of TFT and reproduces device performance with good accuracy.

2:50 p.m.
7.4  Physics-Based Photodiode Model Enabling Consistent Opto-Electronic Circuit Simulation, T. Ezaki, G. Suzuki, K. Konno, O. Matsushima, Y. Mizukane, D. Navarro, M. Miyake, N. Sadachika, H.J. Mattausch, and M. Miura-Mattausch, Hiroshima University, Hiroshima, Japan

We have developed a photodiode model for circuit simulation considering the transient carrier generation. The model is demonstrated to enable accurate simulation of opto-electronic integrated circuit. The electric field distribution along the depth direction causes a tail in the photo current, preventing circuits from fast robust and drift-free switching.

3:15 p.m.
7.5  Noise Modeling in Lateral Asymmetric MOSFET, A.S. Roy, Y.S. Chauhan, C.C. Enz, J.-M Sallese, EPFL, Lausanne, Switzerland

Recently physical modeling of lateral asymmetric (LA) MOSFET, which is the building block of HV devices, has received considerable attention. In this work we show that noise properties of these devices are considerably different from the prediction of conventional Klaassen-Prins (KP) based methods and at low gate voltages, they can overestimate the noise by 2-3 orders of magnitude. We present, for the first time, an analytical noise modeling methodology in presence of lateral asymmetry.

3:40 p.m.
7.6  Performance Boost using a New Device Design Methodology Based on Characteristic Current for Low-Power CMOS, E. Yoshida, Y. Momiyama, M. Miyamoto*, T. Saiki*, M. Kojima*, S. Satoh, T. Sugii, Fujitsu Laboratories Ltd., Akiruno, Japan, *Fujitsu Ltd.,Akiruno, Japan

A characteristic current (I_chr) in CMOS inverter switching has been presented for the first time. I_chr can be adapted from 0.35 um to 65 nm node technology, and so an accurate Tpd can be estimated even for deeper scaled CMOS circuit by using I_chr instead of Ion in CV/I. In addition, by designing the device focusing on I_chr, 15% faster Tpd can be obtained at gate length of 50nm.

4:05 p.m.
7.7  Circuit Technologies for Reducing the Power of SOC and Issues on Transistor Models (Invited), K. Ishibashi, K. Eikyu, T. Tanizawa, S. Ohbayashi, Y. Tsukamoto, H. Mizuno*, M. Miyazaki*, M. Yamaoka*, and K. Osada*, Renesas Technology Corporation, Tokyo, Japan, *Hitachi Ltd., Tokyo, Japan

The obstacles for low power SOC are leakage currents and variability of MOS transistor characteristics. Many circuit techniques have been proposed to tackle these issues. The keys to optimize the circuit design are compact models that handle the leakage and variability. The design technique for SRAM cell is demonstrated.