Session 31: Modeling and Simulation – Compact Modeling
Wednesday, December 15, 9:00 a.m.
Continental Ballroom 5

Co-Chairs: Reinout Woltjer, Philips Research Laboratories Eindhoven
Jin Shyong Jan, UMC

9:00 a.m.
Introduction

9:05 a.m.
31.1  A New Dynamic Cell-Based Performance Metric for Novel CMOS Device Architectures, P. Christie, A. Heringa, G. Doornbos, A. Kumar, V. H. Nguyen, R. K. M. Ng, and M. Garg*, Philips Research, Leuven, Belgium, *Philips Research Laboratories, Eindhoven, The Netherlands

A new performance metric based on statistical layout models and TCAD generated NAND characteristics is compared with existing CV/I-type metrics for system-level NAND circuit performance of bulk and novel low-power 45nm CMOS architectures. The dynamic cell-based metric reveals the superior low-power performance of FDSOI and dual-gate versus bulk architectures.

9:30 a.m.
31.2  Predictive Compact Modeling of NQS Effects and Thermal Noise in 90nm Mixed-Signal/RF CMOS Technology, W.-K. Shih, S. Mudanai, R. Rios, P. Packan, D. Becher, R. Basco, and C. Hung, Intel Corporation, Santa Clara, CA

Predictive compact models have been developed to describe NQS effects and thermal noise in Intel's 90nm radio-frequency (RF) CMOS [1]. The physical approach enables modeling transistor performance from DC to RF with one single set of parameters. Quantum correction on classical induced-gate-noise model is observed for the first time in ultra-thin oxide technology.

9:55 a.m.
31.3  Capacitance Modeling of Laterally Non-Uniform MOS Devices, A.C.T. Aarts, R. van der Hout, J.C.J. Paasschens, A.J. Scholten, M. Willemsen, and D.B.M. Klaassen, Philips Research, Eindhoven, The Netherlands

In this paper the modeling of charging currents in laterally non-uniform MOSFETs, like LDMOS devices, is analyzed. It is shown that no nodal drain and source charge exist for the description of these charging currents. Instead, a capacitance model is derived, and a method is demonstrated to incorporate capacitance-based models into circuit simulators.

10:20 a.m.
31.4  An Efficient Surface Potential Solution Algorithm for Compact MOSFET Models, R. Rios, S. Mudanai, W.-K. Shih, and P. Packan, Intel Corporation, Hillsboro, OR

A critical building block for developing surface-potential based compact MOSFET models is an efficient and accurate solution of the surface potential equation. A robust numerical algorithm, with efficiency comparable to recently proposed analytic approximations but without any compromise in accuracy, is presented in this work.

10:45 a.m.
31.5  Modeling of RTS Noise in MOSFETs Under Steady-State and Large-Signal Excitation, J.S. Kolhatkar, E. Hoekstra, C. Salm, A.P. van der Wel, E.A.M. Klumperink, J. Schmitz, and H. Wallinga, University of Twente, Enschede, The Netherlands

The behavior of RTS noise in MOSFETs under large-signal excitation is experimentally studied. Our measurements show a significant transient effect, in line with earlier reports. We present a new physical model to describe this transient behavior and to predict RTS noise in MOSFETs under large-signal excitation. With only three model parameters the behavior is well described, contrary to existing models.

11:10 a.m.
31.6  A Compact QM-Based Mobility Model for Nanoscale Ultra-Thin-Body CMOS Devices, V. P. Trivedi, J. G. Fossum, and F. Gamiz*, University of Florida, Gainesville, FL, *Universidad de Granada, Granada, Spain

Physical insights, Monte Carlo simulations, and QM- (quantum mechanics) based analysis are used to develop a compact model for effective mobility in ultra-thin-body (UTB) CMOS devices. The model accounts for crucial UTB-thickness dependences, and has only two predominant tuning parameters. It is verified using large sets of experimental data from FD/SOI and SDG MOSFETs.