Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together.  The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors.  The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation:

• Bulk MOS intrinsic models
• SOI/double-gate/multiple-gate/floating-gate MOS models
• Bipolar/HBT/SiGe/GaN/JFET models
• RF/noise/scalable capacitance/NQS models
• Statistical/predictive/process-based models
• Interconnection/passive device models
• Extrinsic/parasitic element models
• Reliability/hot carrier/tunneling/ESD models
• Atomic-level/quantum-mechanical compact models
• Numerical/TCAD/behavioral/table-based models
• Model parameter extraction and optimization
• Model-simulator interface and standardization

• Narain Arora, Cadence Design Systems, USA
• Matthias Bucher, Technical University of Crete, Greece
• Mansun Chan, Hong Kong University of Science and Technology, Hong Kong
• Zuhui Chen, Xiamen University, China
• Jamal Deen, McMaster University, Canada
• Robert Dutton, Stanford University, USA
• Tor Fjeldly, Norwegian University of Science and Technology, Norway
• Jerry Fossum, University of Florida, USA
• Carlos Galup-Montoro, Universidade Federal de Santa Catarina, Brazil
• Chenming Hu, University of California at Berkeley, USA
• Benjamín Iñíguez, Universitat Rovira i Virgili, Spain
• Bin Jie, Peking University, China
• Dirk Klaassen, NXP Semiconductors, The Netherlands
• Mark Lundstrom, Purdue University, USA
• Colin McAndrew, Freescale Semiconductor, USA
• Mitiko Miura-Mattausch, Hiroshima University, Japan
• Adelmo Ortiz-Conde, Universidad Simón Bolívar, Venezuela
• Chih-Tang Sah, University of Florida, USA
• Michael Schröter, University of Technology Dresden, Germany
• Yuan Taur, University of California at San Diego, USA
• Josef Watts, IBM, USA
• Philip Wong, Stanford University, USA
• Xing Zhou, Nanyang Technological University, Singapore

There are 23 invited papers, which are categorized in the following topic areas:

Bulk MOS intrinsic models

• Design-Oriented Characterization and Parameter Extraction Methodologies for the EKV3 MOSFET Model

Matthias Bucher, Technical University of Crete, GR
• Consistency of Compact MOSFET Models with the Pao-Sah Formulation: Consequences for Small-signal Analysis

Carlos Galup-Montoro, Universidade Federal de Santa Catarina, BR
• Analytical Solutions for Long-Wide-Channel MOS Transistors With Spatially Varying Impurity Concentrations

Bin Jie, Peking University, CN
• HiSIM2.4.0: Advanced MOSFET Model for the 45nm Technology Node and Beyond

Mitiko Miura-Mattausch, Hiroshima University, JP

• High Conentration of Interface Traps in MOS Transistor Modeling

Zuhui Chen, Xiamen University, CN
• A History of Electronic Traps on Silicon Surfaces and Interfaces

Chih-Tang Sah, University of Florida, US

• Compact Modeling Framework for Short-Channel DG and GAA MOSFETs

Tor Fjeldly, Norwegian University of Science and Technology, NO
• Modeling of Saturation-Region Characteristics of Nanoscale Double-Gate MOSFETs

Jerry Fossum, University of Florida, US
• A Versatile Multigate MOSFET Compact Model: BSIM-MG

Chenming Hu, University of California at Berkeley, US
• 3-D Analytical Models for the Short-Channel Effect Parameters in Undoped FinFET Devices

Benjamín Iñíguez, Universitat Rovira i Virgili, ES
• A PSP Based Scalable Compact FinFET Model

Dirk Klaassen, Philips Research Laboratories, NE
• A Unified View of Drain Current Models for Undoped Double-Gate SOI MOSFETs

Adelmo Ortiz-Conde, Universidad Simón Bolívar, VE
• Analytic Charge Model for Double-Gate and Surrounding-Gate MOSFETs

Yuan Taur, University of California at San Diego, US
• Unified Compact Model for Generic Double-Gate MOSFETs

Xing Zhou, Nanyang Technological University, SG

• Nanoscale Physics for Compact Models

Mark Lundstrom, Purdue University, US
• Carbon Nanotube Transistor Compact Model

Philip Wong, Stanford University, US

• Modeling of FET Flicker Noise and Impact of Technology Scaling

Robert Dutton, Stanford University, US

• Analysis of Halo Implanted MOSFETs

Colin McAndrew, Freescale Semiconductor, US
• Modeling MOSFET Process Variation Using PSP

Josef Watts, IBM, US

• RCL Modeling and Characterization of X Architecture Diagonal Lines for Sub-100nm SoC Design 

Narain Arora, Cadence Design Systems, US

• Modeling the Geometry-Dependent Parasitics in Multi-Fin FinFETs

Mansun Chan, Hong Kong University of Science and Technology, HK

• Modeling the Electrical Characteristics of FET-type Sensors for Biomedical Applications

Jamal Deen, McMaster University, CA

• Non-standard Geometry Scaling Effects

Michael Schröter, University of Technology Dresden, DE

See Nanotech website for instructions for authors:

See Nanotech website for conference registration:

• Double-Gate Thin-Base MOS Transistor: The Correct Theory
• Double-Gate Thin-Base MOS Transistor: Characteristics for the Long Channel
• U-Shaped Engery Distribution of Electronic Interface Traps on Oxidized Silicon

• Monolithic Concept and the Inventions of Integrated Circuits by Kilby and Noyce