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Workshop on Compact Modeling at the 9th International Conference on Modeling and Simulation of Microsystems

Date	May 9-11, 2006
Venue	Hynes Convention Center Boston, Massachusetts, USA
Synopsis	Compact Models (CMs) for circuit simulation have been at the heart of CAD tools for circuit design over the past decades, and are playing an ever increasingly important role in the nanometer system-on-chip (SOC) era. As the mainstream MOS technology is scaled into the nanometer regime, development of a truly physical and predictive compact model for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge. Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective of WCM is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development and deployment, within the main theme - compact models for circuit simulation: Bulk MOS intrinsic models SOI/double-gate/multiple-gate/floating-gate MOS models Bipolar/HBT/SiGe/GaN/JFET models RF/noise/scalable capacitance/NQS models Statistical/predictive/process-based models Interconnection/passive device models Extrinsic/parasitic element models Reliability/hot carrier/tunneling/ESD models Atomic-level/quantum-mechanical compact models Numerical/TCAD/behavioral/table-based models Model parameter extraction and optimization Model-simulator interface and standardization	top
Invited Speakers	Invited speakers from all over the world are listed below: Matthias Bucher, Technical University of Crete, Greece Robert Dutton, Stanford University, USA Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland Tor Fjeldly, Norwegian University of Science and Technology, Norway Jerry Fossum, University of Florida, USA Carlos Galup-Montoro, Universidade Federal de Santa Catarina, Brazil Gennady Gildenblat, Pennsylvania State University, USA John Hauser, North Carolina State University, USA Jin He, Peking University, China Chenming Hu and Mohan Dunga, University of California at Berkeley, USA Benjamín Iñíguez, Universitat Rovira i Virgili, Spain Dirk Klaassen, Philips Research Laboratories, The Netherlands Shiuh-Wuu Lee and Sivakumar Mudanai, Intel, USA Juin Liou, University of Central Florida, USA Ramana Malladi, IBM, USA Colin McAndrew, Freescale Semiconductor, USA Mitiko Miura-Mattausch and Tatsuya Ezaki, Hiroshima University, Japan Fabien Prégaldiny, InESS, France Chih-Tang Sah and Bin Jie, University of Florida, USA Michael Schröter, University of Technology Dresden, Germany Ehrenfried Seebacher, Austriamicrosystems AG, Austria Michael Shur, Rensselaer Polytechnic Institute, USA Josef Watts, IBM, USA Man Wong, Hong Kong University of Science and Technology, Hong Kong Yuan Taur, University of California at San Diego, USA Xing Zhou, Nanyang Technological University, Singapore	top
Workshop Program	WCM2006 Program has been posted at the following web: http://www.nsti.org/Nanotech2006/WCM2006/ There are 27 invited papers, which are categorized in the following topic areas: *Bulk MOS intrinsic models* Carrier Generation and Recombination Currents At Interface Traps In Long-Channel Surface-Potential-Based MOS Transistor Compact Chih-Tang Sah, University of Florida, US Recent Advances in the EKV3.0 MOSFET Model Matthias Bucher, Technical University of Crete, GR Symbolic Charge-based MOSFET Model Carlos Galup-Montoro, Universidade Federal de Santa Catarina, BR Theory and Modeling Techniques Used in PSP Model Gennady Gildenblat, Pennsylvania State University, US An MOS Model with an Improved Mobility Model John Hauser, North Carolina State University, US Benchmark Tests on Conventional Surface Potential Based Charge-Sheet Models and PUNSIM Development Jin He, Peking University, CN Accuracy of Long-Channel Surface-Potential-Based MOS Transistor Compact Models Bin Jie, University of Florida, US Advanced Compact MOSFET Model HiSIM2 Based Surface Potentials with a Minimum Number of Approximations Mitiko Miura-Mattausch, Hiroshima University, JP Halo Doping: Physical Effects and Compact Modeling Sivakumar Mudanai, Intel, US Compact Iterative Field Effect Transistor Model Michael Shur, Rensselaer Polytechnic Institute, US Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling Xing Zhou, Nanyang Technological University, SG *Double/multiple-gate MOS models* BSIM4 and BSIM Multi-Gate Progress Mohan Dunga, University of California at Berkeley, US A Charge-Based Compact Model of Double Gate MOSFET Christian Enz, Swiss Center for Electronics and Microtechnology, CH Precise 2D Compact Modeling of Nanoscale DG MOSFETs Based on Conformal Mapping Techniques Tor Fjeldly, Norwegian University of Science and Technology, NO Recent Upgrades and Applications of UFDG Jerry Fossum, University of Florida, US DC to RF Small-Signal Compact DG MOSFET Model Benjamín Iñíguez, Universitat Rovira i Virgili, ES An Explicit Quasi-static Charge-based Compact Model for Symmetric DG MOSFET Fabien Prégaldiny, InESS, FR On the Modeling of the Current-Voltage Characteristics of a Symmetrical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with an Undoped Body Man Wong, Hong Kong University of Science and Technology, HK Compact Modeling of Short-channel Double-gate MOSFETs Yuan Taur, University of California at San Diego, US *Statistical modeling* Device Correlation: Modeling using Uncorrelated Parameters, Characterization Using Ratios and Differences Colin McAndrew, Freescale Semiconductor, US Modeling Small MOSFETs Using Ensemble Devices Josef Watts, IBM, US *TCAD-based RF models* Effects of Scaling on Modeling of Analog RF MOS Devices Robert Dutton, Stanford University, US *High-voltage/LDMOS models* High-Voltage LDMOS Compact Modeling Dirk Klaassen, Philips Research Laboratories, NE Analog Compact Modeling for a 20-120V HV CMOS Technology Ehrenfried Seebacher, Austriamicrosystems AG, AT *Interconnect models* Compact Modeling of Spiral Inductors for RF Applications Juin Liou, University of Central Florida, US *Bipolar/HBT models* Development and Design Kit Integration of a Scalable and Statistical High Current Model for Advanced SiGe HBTs Ramana Malladi, IBM, US Charge-storage Calculation for Si-based Bipolar Transistors from Device Simulation Michael Schröter, University of Technology Dresden, DE	top
Poster Session	Poster presentations in the scope of "compact models for circuit simulation" are solicited. Please note that only posters submitted to WCM will be considered. A 5-minute oral briefing for each poster paper is planned. See Nanotech website for instructions for authors: http://www.nsti.org/Nanotech2006/authors/ There are 35 contributed poster papers, which are listed below (speakers underlined). Improved Basic Symmetry Tests for MOSFET Models C. McAndrew, Freescale Semiconductor, US Scalable MOSFET Short-channel Charge Model in All Regions G.H. See, S.B. Chiah, X. Zhou, K. Chandrasekaran, W. Shangguan, Z. Zhu, G.H. Lim, S.M. Pandey, M. Cheng, S. Chu, and L-C Hsia, Nanyang Technological University, SG Compact Modeling of Nonlinearities in Submicron MOSFETs P.D. da Silva, F.R. de Sousa, C.G. Montoro and M.C. Schneider, Federal University of Santa Catarina, BR Charge-Based Formulation of Thermal Noise in Short-Channel MOS Transistors V.C. Paim, C. Galup-Montoro and M.C. Schneider, Federal University of Santa Catarina, BR On the Compact Modelling of Induced Gate Noise in the MOS Transistor A.S. Roy and C.C. ENz, Swiss Federal Institute of Technology, Lausanne (EPFL), CH Low-Frequency and RF Performance of Schottky-Diode for RFIC Applications and the Observation of RTS Noise Characteristics Y.Z. Xiong, G.Q. Lo, J.L. Shi, M.B. Yu, W.Y. Loh and D.L. Kwong, Institute of Microelectronics, SG Two-Tone Distortion Modeling for SiGe HBTs Using the High-Current Model R. Malladi, V. Borich, S.L. Sweeney, J. Rascoe, K.M. Newton, S. Venkatadri, J. Yang and S. Chen, IBM Systems and Technology, US BSIM Model for MOSFET Flicker Noise Statistics: Technology Scaling, Area, and Bias Dependence M. Erturk, R. Anna, J.C. Lee, L.H. Pan, J.R. Jones, K.M. Newton, T. Xia and C.J. LaMothe, IBM Systems and Technology, US Investigation of Substrate Current Effects and Modeling of Substrate Resistance Network for RFCMOS J.C. Lee, R.B. Anna, L.H. Pan and K.M. Newton, IBM Systems and Technology, US NQS Effects in MOSFET's and its Implementation in Advanced Compact Models Y. Ma, M-C Jeng and Z. Liu, Cadence Design Systems, US Capacitance Modeling for LDMOS Y. Ma, P. Chen, M-C Jeng and Z. Liu, Cadence Design Systems, US TCAD-based Process Dependant HSPICE Model Parameter Extraction Y. Mahotin and S. Tirumala, Synopsys, US A Carrier Based Analytic Model for Undoped Surrounding-Gate MOSFETs J. He, Z. Xing, G. Zhang and Y. Wang, Peking University, CN Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach Z.M. Zhu, K. Chandrasekaran, X. Zhou, W. Shangguan, G.H. See, S.B. Chiah, S.C. Rustagi and N. Singh, Nanyang Technological University, SG Explicit Compact Model of Independent Double Gate MOSFET M. Reyboz, O. Rozeau, T. Poiroux, P. Martin and J. Jomaah, CEA, FR Capacitance Model for Four-Terminal DG MOSFETs T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki, S. O’uchi and H. Koike, National Institute of Advanced Industrial Science and Technology, JP A Computationally Efficient Method for Analytical Calculation of Potentials in Undoped Symmetric DG SOI MOSFET O. Cobianu and M. Glesner, Darmstadt University of Technology, DE Compact Model of Drain-Current in Double-Gate MOSFETs Including Carrier Quantization and Short-channel Effects X. Loussier, D. Munteanu, J.L. Autran, S. Harrison and R. Cerutti, L2MP, FR Performance Analysis of Double-Gate MOSFET-based Circuits Using a Compact Model Implemented in Eldo IC Analog Simulator O. Tintori, X. Loussier, D. Munteanu, J.L. Autran, A. Regnier and R. Bouchakour, L2MP, FR Comparison of Three Region Multiple Gate Nanoscale Structures for Reduced Short Channel Effects and High Device Reliability K. Goel, M. Saxena, M. Gupta and R.S. Gupta, University of Delhi South Campus, IN Compact Model for Short Channel Effects in Source/Drain Engineered Nanoscale Double Gate (DG) SOI MOSFETs A. Kranti and G.A. Armstrong, Queen's University of Belfast, UK Compact Models for Double Gate and Surrounding Gate MOSFETs H. Abebe, E. Cumberbatch, H. Morris and S. Uno, San Jose State University, US SOI CMOS Compact Modeling Based on TCAD Device Simulations A. Botula, S. Furkay, D.C. Sheridan, J.M. Johnson and M-H Na, IBM Corporation, US On Idlow with Emphasis on Speculative SPICE Modeling Q. Chen, Z-Y Wu, A.B. Icel, J-S Goo, S. Krishnan, C. Thuruthiyil, N. Subba, S. Suryagandh, J.X. An, T. Ly, M. Radwin, J. Yonemura and F. Assad, Advanced Micro Devices, US Dynamic Behavior Model for High-K MOSFETs M.V. Dunga, X. Xi, A.M. Niknejad and C. Hu, University of California, Berkeley, US A Simple Yet Accurate Mismatch Model for Circuit simulation Z. Jin, Y-M Lee, J. Watts, A. Bonaccio, G. Schroer and N. Pai, IBM, US Enhanced Junction Depletion Capacitance Modeling F.G. Anderson, R.M. Rassel and M.A. Lavoie, IBM Microelectronics, US A Compact Model of Ballistic CNFET for Circuit Simulation B.C. Paul, S. Fujita, M. Okajima and T. Lee, Toshiba America Research, JP A Circuit-Compatible Model of Ballistic Silicon Nanowire Transistors J. Chen, Agere Systems, US Compact Modeling of Threshold Voltage in Nanoscale Strained-Si/SiGe MOSFETs S. Nawal, V. Venkataraman and M.J. Kumar, Indian Institute of Technology, New Delhi, IN Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90nm SOI ULSI Technology R.Q. Williams, D. Chidambarrao, J.H. McCullen, S. Narasimha, T.G. Mitchell and D. Onsongo, IBM Corporation, US A Transient Lumped Element Model for a Phase Change Circuit Memory Element H.G.A. Huizing, D. Tio Castro, J.C.J. Paasschens and M.H.R. Lankhorst, Philips, NL Static Analog Design Methodology F. Guigues, F. Rudolff and E. Kussener, L2MP UMR 6137 CNRS - ISEN-Toulon, FR Interrelations Between Threshold Voltage Definitions and Extraction Methods M.C. Schneider, C. Galup-Montoro, M.B. Machado and A.I.A. Cunha, Federal University of Santa Catarina, BR A Unified Parameter Extraction Procedure for Scalable Bipolar Transistor Model Mextram H-C Wu, S. Mijalkovic and J.N. Burghartz, Delft University of Technology, NL	top
Presentation Slides	(Click on each to download the PDF file. © Copyright of the PDF files belongs to the respective contributors. Last update: August 5, 2006.) Download and save the entire ZIP file of presentation slides (27MB) Xing Zhou, Opening Remark
Invited	Chih-Tang Sah, Carrier Generation and Recombination Currents At Interface Traps In Long-Channel Surface-Potential-Based MOS Transistor Compact Carlos Galup-Montoro, Symbolic Charge-based MOSFET Model Gennady Gildenblat, Theory and Modeling Techniques Used in PSP Model John Hauser, An MOS Model with an Improved Mobility Model Jin He, Benchmark Tests on Conventional Surface Potential Based Charge-Sheet Models and PUNSIM Development Bin Jie, Accuracy of Long-Channel Surface-Potential-Based MOS Transistor Compact Models Mitiko Miura-Mattausch, Advanced Compact MOSFET Model HiSIM2 Based Surface Potentials with a Minimum Number of Approximations Sivakumar Mudanai, Halo Doping: Physical Effects and Compact Modeling Michael Shur, Compact Iterative Field Effect Transistor Model Xing Zhou, Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling Mohan Dunga, BSIM4 and BSIM Multi-Gate Progress Christian Enz, A Charge-Based Compact Model of Double Gate MOSFET Tor Fjeldly, Precise 2D Compact Modeling of Nanoscale DG MOSFETs Based on Conformal Mapping Techniques Jerry Fossum, Recent Upgrades and Applications of UFDG Fabien Prégaldiny, An Explicit Quasi-static Charge-based Compact Model for Symmetric DG MOSFET Man Wong, On the Modeling of the Current-Voltage Characteristics of a Symmetrical Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor with an Undoped Body Colin McAndrew, Device Correlation: Modeling using Uncorrelated Parameters, Characterization Using Ratios and Differences Josef Watts, Modeling Small MOSFETs Using Ensemble Devices Yang Liu, Effects of Scaling on Modeling of Analog RF MOS Devices Dirk Klaassen, High-Voltage LDMOS Compact Modeling Ehrenfried Seebacher, Analog Compact Modeling for a 20-120V HV CMOS Technology Juin Liou, Compact Modeling of Spiral Inductors for RF Applications Field-Effect Transistors Ramana Malladi, Development and Design Kit Integration of a Scalable and Statistical High Current Model for Advanced SiGe HBTs Michael Schröter, Charge-storage Calculation for Si-based Bipolar Transistors from Device Simulation Matthias Bucher, Recent Advances in the EKV3.0 MOSFET Model
Posters	Colin McAndrew, Improved Basic Symmetry Tests for MOSFET Models Guan Huei See, Scalable MOSFET Short-channel Charge Model in All Regions Marcio Schneider, Compact Modeling of Nonlinearities in Submicron MOSFETs Marcio Schneider, Charge-Based Formulation of Thermal Noise in Short-Channel MOS Transistors A. S. Roy, On the Compact Modelling of Induced Gate Noise in the MOS Transistor Ramana Malladi, Two-Tone Distortion Modeling for SiGe HBTs Using the High-Current Model M. Erturk, BSIM Model for MOSFET Flicker Noise Statistics: Technology Scaling, Area, and Bias Dependence J.C. Lee, Investigation of Substrate Current Effects and Modeling of Substrate Resistance Network for RFCMOS Yutao Ma, NQS Effects in MOSFET's and its Implementation in Advanced Compact Models Yutao Ma, Capacitance Modeling for LDMOS Yuri Mahotin, TCAD-based Process Dependant HSPICE Model Parameter Extraction Jin He, A Carrier Based Analytic Model for Undoped Surrounding-Gate MOSFETs Karthik Chandrasekaran, Compact Modeling of Doped Symmetric DG MOSFETs with Regional Approach Marina Reyboz, Explicit Compact Model of Independent Double Gate MOSFET T. Nakagawa, Capacitance Model for Four-Terminal DG MOSFETs X. Loussier, Compact Model of Drain-Current in Double-Gate MOSFETs Including Carrier Quantization and Short-channel Effects O. Tintori, Performance Analysis of Double-Gate MOSFET-based Circuits Using a Compact Model Implemented in Eldo IC Analog Simulator G. Alastair Armstrong, Compact Model for Short Channel Effects in Source/Drain Engineered Nanoscale Double Gate (DG) SOI MOSFETs H. Abebe, Compact Models for Double Gate and Surrounding Gate MOSFETs A. Botula, SOI CMOS Compact Modeling Based on TCAD Device Simulations Qiang Chen, On Idlow with Emphasis on Speculative SPICE Modeling Mohan Dunga, Dynamic Behavior Model for High-K MOSFETs Zhenrong Jin, A Simple Yet Accurate Mismatch Model for Circuit simulation F. G. Anderson, Enhanced Junction Depletion Capacitance Modeling B. C. Paul, A Compact Model of Ballistic CNFET for Circuit Simulation Richard Williams, Compact Model Methodology for Dual-Stress Nitride Liner Films in a 90nm SOI ULSI Technology F. Guigues, Static Analog Design Methodology Ana Cunha, Interrelations Between Threshold Voltage Definitions and Extraction Methods H.-C. Wu, A Unified Parameter Extraction Procedure for Scalable Bipolar Transistor Model Mextram
Websites for Proceedings	http://www.nsti.org/procs/Nanotech2006v3/7
WCM-MSM2006 official websites	http://www.nsti.org/Nanotech2006/WCM2006/
WCM2005 website	View 2005 WCM program and presentation slides
WCM2004 website	View 2004 WCM program and presentation slides
WCM2003 website	View 2003 WCM program and presentation slides
WCM2002 website	View 2002 WCM program and presentation slides

(Updated: August 5, 2006)