WCM - Workshop on Compact Modeling

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Workshop on Compact Modeling at the 5th International Conference on Modeling and Simulation of Microsystems

Date	April 23-25, 2002
Venue	San Juan Marriot Resort & Stellaris Casino San Juan, Puerto Rico, USA
Synopsis	As the mainstream MOS technology is scaled into the very-deep-submicron (VDSM) era, development of a truly physical and predictive MOSFET compact model (CM) for circuit simulation that covers geometry, bias, temperature, DC, AC, RF, and noise characteristics becomes a major challenge. There exist a large number of CM development efforts that address the new challenges in theoretical models as well as industrial applications. It would be beneficial to bring together researchers and CM developers to share their ideas and insights on the current needs and future trends in CM development in the context of VDSM technology and circuit as well as system-on-chip (SOC) design. Workshop on Compact Modeling (WCM) is one of the first of its kind in bringing people in the CM field together. The objective is to create a truly open forum for discussion among experts in the field as well as feedback from technology developers and circuit designers. It consists of a 2 day Invited-Speaker Session, an Evening Panel Session, and a Tutorial Session. Regular papers are also solicited to follow the above sessions in the Contributed-Paper Session. The topics are centered at bulk-Si and SOI MOSFET compact models for circuit simulation to address the following issues: Physics-based I-V model formulations Scalable AC/RF/noise models Predictive models with process correlation Statistical modeling with compact models Compact model with higher-order (atomic-level) effects Parameter extraction Global vs local optimization Equivalent circuit generation from numerical simulation Compact solution from surface-potential-based models Benckmark tests and model comparisons Compact models for SOI MOSFETs Interconnect modeling in CMOS technology Role of CM in bridging technology development, TCAD, and circuit design Trends and needs in compact models in the VDSM era	top
Invited Speakers	There are 23 invited speakers from all over the world (10 countries) to present their work and their views on compact modeling. They are listed below: Narain Arora, Simplex Solutions, USA Peter Bendix, LSI Logic, USA Britt Brooks, Texas Instruments, USA Matthias Bucher, National Technical University of Athens, Greece Mansun Chan, Hong Kong University of Science and Technology, Hong Kong Jamal Deen, McMaster University, Canada Michael Duane, Applied Materials, USA Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland Jerry Fossum, University of Florida, USA Daniel Foty, Gilgamesh Associates, USA Samuel Fung, IBM, USA Gennady Gildenblat, Pennsylvania State University, USA Dirk Klaassen, Philips Research Laboratories, The Netherlands Kwyro Lee, Korea Advanced Institute of Science and Technology, Korea Serge Luryi, State University of New York at Stony Brook, USA Marco Mastrapasqua, Agere Systems, USA Colin McAndrew, Motorola, USA Mitiko Miura-Mattausch, Hiroshima University, Japan Andrea Pacelli, State University of New York at Stony Brook, USA Roberto Suaya, Mentor Graphics, France Josef Watts, IBM, USA Xisheng Zhang, Celestry Design Technologies, USA Xing Zhou, Nanyang Technological University, Singapore	top
Workshop Program	WCM-1: Tuesday, April 23, 10:30 - 12:00 Session chair: Xing Zhou, Nanyang Technological University, Singapore Challenges of Modeling VLSI Interconnects in the DSM Era Narain Arora, Simplex Solutions, USA Detailed Comparison of the SP, EKV, and BSIM3 Models Peter Bendix, LSI Logic, USA Standardization and Validation of Compact Models Britt Brooks, Texas Instruments, USA WCM-2: Tuesday, April 23, 14:00 - 15:30 Session chair: Jerry Fossum, University of Florida, USA Advanced Surface-Potential-Based Model (SP) Gennady Gildenblat, Pennsylvania State University, USA Engineering BSIM for the Nano-Technology Era and Beyond Mansun Chan, Hong Kong University of Science and Technology, Hong Kong The Foundations of the EKV MOS Transistor Charge-Based Model Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland WCM-3: Tuesday, April 23, 16:00 - 18:00 Session chair: Serge Luryi, State University of New York at Stony Brook, USA The EKV Compact MOS Transistor Model Version 3: Accounting for Deep-Submicron Aspects Matthias Bucher, National Technical University of Athens, Greece RF Applications of MOS Model 11 Dirk Klaassen, Philips Research Laboratories, The Netherlands HiSIM: Self-Consistent Surface-Potential MOS-Model Valid Down to Sub-100nm Technologies Mitiko Miura-Mattausch, Hiroshima University, Japan Starting Over: gms/Id-based MOSFET Modeling as a Basis for Modernized Analog Design Methodologies Daniel Foty, Gilgamesh Associates, USA WCM-4: Wednesday, April 24, 8:30 - 10:00 Session chair: Narain Arora, Simplex Solutions, USA A Unified Process-Based Compact Model for Scaled PD/SOI and Bulk-Si MOSFETs Jerry Fossum, University of Florida, USA Measurements and Modeling of Mobility in Ultra-Thin SOI Marco Mastrapasqua, Agere Systems, USA RF MOS Noise Parameter Extraction and Modeling Jamal Deen, McMaster University, Canada WCM-5: Wednesday, April 24, 10:30 - 12:00 Session chair: Christian Enz, CSEM SA, Switzerland RF CMOS Modeling and Parameter Extraction Approaches Taking Charge Conservation into Account Kwyro Lee, Korea Advanced Institute of Science and Technology, Korea Automatic Generation of RF Compact Models from Device Simulation Serge Luryi and Andrea Pacelli, State University of New York at Stony Brook, USA Part I: Motivation and methodology (by Serge Luryi) Part II: Implementation and applications (by Andrea Pacelli) WCM-6: Wednesday, April 24, 14:00 - 15:30 Session chair: Jamal Deen, McMaster University, Canada Xsim: A Compact Model for Bridging Technology Developers and Circuit Designers Xing Zhou, Nanyang Technological University, Singapore Unified Statistical Modeling for Circuit Simulation Colin McAndrew, Motorola, USA The Role of TCAD in Compact Modeling Michael Duane, Applied Materials, USA WCM-7: Wednesday, April 24, 15:40 - 17:40 Session chair: Dirk Klaassen, Philips Research Laboratories, The Netherlands Interconnect Modeling for High Speed Digital Circuits - the Role of RLC Coupling Roberto Suaya, Mentor Graphics, France How to Build an SOI MOSFET Compact Model without Violating the Laws of Physics Josef Watts, IBM, USA Simulation Study of Non-Quasi Static Behaviour of MOS Transistors (contributed) D. V. Kumar, M. B. Patil, and V. R. Rao, Indian Institute of Technology - Bombay, India WCM-8: Thursday, April 25, 9:30 - 11:00 Session chair: Albert Kordesch, Silterra Malaysia Present Status and Future Direction of BSIM SOI Model for High-Performance/Low-Power/RF Application Samuel Fung, IBM, USA A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling (contributed) L. Larcher and P. Pavan, Università di Modena e Reggio Emilia, Italy Compact Model for Manufacturing Design and Fluctuation Study (contributed) K. Y. Lim and X. Zhou, Chartered Semiconductor Manufacturing Ltd., Singapore Physically-Based Approach to Deep-Submicron MOSFET Compact Model Parameter Extraction (contributed) S. B. Chiah, X. Zhou, K. Y. Lim, A. See, and L. Chan, Nanyang Technological University, Singapore	top
Evening Panel Session	*Trends and Needs in Compact Models in the SOC Era* Tuesday, April 23, 19:00 - 21:00
Moderator	Narain Arora, Simplex Solutions, USA
Panelist	Peter Bendix, LSI Logic, USA Britt Brooks, Texas Instruments, USA Mansun Chan, Hong Kong University of Science and Technology, Hong Kong Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland Daniel Foty, Gilgamesh Associates, USA Gennady Gildenblat, Pennsylvania State University, USA Dirk Klaassen, Philips Research Laboratories, The Netherlands Mitiko Miura-Mattausch, Hiroshima University, Japan
Agenda	A) 19:00 – 19:45: 5-min presentation for each panelist for the individual personal views on the topic: "Trends and Needs in Compact Models in the SOC Era" B) 19:45 – 20:30: Panel discussion on the selected 8 topics (average ~10min/topic). Panelists are to provide their views on the pros and cons, supporting or opposing arguments for the following topic categories: Compact model standardization vs. diversity Compact model quality: definitions and priorities Compact model applications in circuit design and technology development Compact model parameter extraction vs. optimization Compact model predictability and scalability RF/parasitic/interconnect models vs. intrinsic transistor compact models Compact model accuracy and efficiency tradeoff Physically based vs. largely empirical compact models C) 20:30 – 21:00: Q/A session for the audience	top
Tutorial Session	Thursday, April 25, 11:00 - 18:15
	Five tutorials are offered by the invitees on special topics, which are arranged in series with the Invited-Speaker Session for the general audience. Model Equations of the Self-Consistent Surface-Potential MOS-Model HiSIM Mitiko Miura-Mattausch, Hiroshima University, Japan Submicron Circuit Design with BSIM3/4 Mansun Chan, Hong Kong University of Science and Technology, Hong Kong MOS Transistor Modeling for RF IC Design Christian Enz, Swiss Center for Electronics and Microtechnology, Switzerland MOS Modeling, Design Quality, and Modern Analog Design Daniel Foty, Gilgamesh Associates, USA An Introduction to MOS Model 11 Dirk Klaassen, Philips Research Laboratories, The Netherlands	top
Presentation Slides	(Click on each to download the PDF file. © Copyright of the PDF files belongs to the respective contributors.) Download and save the entire ZIP file of presentation slides (18MB) Narain Arora, Challenges of Modeling VLSI Interconnects in the DSM Era Peter Bendix, Detailed Comparison of the SP, EKV, and BSIM3 Models Mansun Chan, Engineering BSIM for the Nano-Technology Era and Beyond Jamal Deen, RF MOS Noise Parameter Extraction and Modeling Michael Duane, The Role of TCAD in Compact Modeling Christian Enz, The Foundations of the EKV MOS Transistor Charge-Based Model Jerry Fossum, A Unified Process-Based Compact Model for Scaled PD/SOI and Bulk-Si MOSFETs Samuel Fung, Present Status and Future Direction of BSIM SOI Model for High-Performance/Low-Power/RF Application Gennady Gildenblat, Advanced Surface-Potential-Based Model (SP) Dirk Klaassen, RF Applications of MOS Model 11 Kwyro Lee, RF CMOS Modeling and Parameter Extraction Approaches Taking Charge Conservation into Account Serge Luryi, Automatic Generation of RF Compact Models from Device Simulation - Part I: Motivation and methodology Colin McAndrew, Unified Statistical Modeling for Circuit Simulation Mitiko Miura-Mattausch, HiSIM: Self-Consistent Surface-Potential MOS-Model Valid Down to Sub-100nm Technologies Andrea Pacelli, Automatic Generation of RF Compact Models from Device Simulation - Part II: Implementation and applications Josef Watts, How to Build an SOI MOSFET Compact Model without Violating the Laws of Physics Xing Zhou, Xsim: A Compact Model for Bridging Technology Developers and Circuit Designers S. B. Chiah, Physically-Based Approach to Deep-Submicron MOSFET Compact Model Parameter Extraction D. V. Kumar, Simulation Study of Non-Quasi Static Behaviour of MOS Transistors L. Larcher, A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling K. Y. Lim, Compact Model for Manufacturing Design and Fluctuation Study	top
Closing Remark	Thursday, April 25, 18:15 - 18:30
	Xing Zhou, Nanyang Technological University, Singapore	top
Websites for Proceedings	http://nsti.org/procs/MSM2002/13

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