A process compact model (PCM) provides the link between process parameters and device (performance) characteristics. Process compact models capture the process–device relationships between the process parameters and device performance of a semiconductor manufacturing process. They are robust, fast to evaluate, and can be embedded into other environments, such as spreadsheet applications and yield management systems. The PCMs are analogous to device compact models, which capture electrical behavior and can be derived from measurements or simulations. They also form the basis for further statistical analysis of data in combination with measured data.
TCAD simulations run quite fast for 2D process and device structures. However, 3D process and device simulations can take up to several days to run. Thus, it is interesting to build up compact model for 3D process effects and their implication on the device performance.

In this project, we propose to develop a strategy to minimize the number of 3D simulations for catching the effect of the process on the device using compact modeling. The physics of the process and MOS device must be well understood as well as the different analytical models used to characterize the MOS transistors.
The goal of this project is to evaluate the minimal number of 3D simulations needed to build up a compact model, which can predict the impact of the process on the device. This minimum number of 3D simulations is complementary to the 2D simulations used to determine the parameters of the compact models independent on the width of the transistor.