This NTU-TUM joint PhD project is directed towards the development of analytic models for reliability and variability of CMOS circuits at the transistor and gate levels.  Major reliability issues in MOS transistors will be captured in the physics-based compact models and propagated to the gate-level.  A multi-level modeling approach will be adopted in which the higher-level (gate) model corresponds to, and its parameters being extracted from, the lower-level (transistor) equivalent.  The ultimate goal is to have device reliability and variability captured and incorporated into the circuit/logic design rather than assessing them after the design based on ideal device characteristics.  The specific aims of this joint PhD project are:
- Develop transistor degradation compact models for use in gate-level aging analysis and timing predictions;
- Apply transistor compact models for statistical parametric variations to gate-level abstraction for use in variability-aware designs.

(Back)