This project is directed towards the development of a TCAD-synthesis approach to deep-submicron MOS technology characterisation and modelling.  Emulation of a real wafer fabrication process and transistor electrical characterisation will be carried out through extensive simulation using the state-of-the-art technology computer-aided design (TCAD) tools, in which structural nonuniformities and transport nonlinearities are modelled.  Simulation will be correlated to experimental data by providing a guide to technology developers to bracket the final optimum design.  Combined with a physical-based compact model, this approach will demonstrate a first attempt at bridging technology development to circuit design in the deep-submicron era.

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