High-voltage (HV) transistors are used in RF/microwave power amplifiers.  In standard CMOS-compatible technologies, various HV transistor structures are available, such as laterally-diffused metal oxide semiconductor (LDMOS) and extended-drain MOSFETs (EDMOS).  GaN-on-Si HV transistors with different gate structures (Schottky or insulated-gate) are also emerging.

For designing RF integrated circuits with HV and high-power device building blocks, a compact model for these HV transistors is needed, with parameters specific to HV devices and general to CMOS processes.  Unlike conventional MOSFETs which are ideally symmetric devices, HV transistors are usually designed with asymmetric source/drain.  Special efforts are needed in modeling charges and capacitances with lateral nonuniformities based on conventional surface-potential based models.  This project is directed towards developing HV transistor compact models for use in RF circuit designs.  DC, AC, and geometry/temperature dependencies of HV transistor models will be developed and validated with numerical and experimental devices.  A unified approach will be adopted to incorporate various HV transistor structures into the model.

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