ACRS Online Journal Publications

Journal of Modeling and Simulation of Microsystems, JMSM
ISSN# 1524-2021		 Vol. 2., No., 1.
Paper# 2/01779
Title: Physics-Based Threshold Voltage Modeling with Reverse Short Channel Effect
Author(s): K-Y Lim, X. Zhou, and Y. Wang
Affiliation: School of Electrical & Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798
Keywords: RSCE, lateral non-uniform profile, threshold voltage, compact model, MOSFET
Abstract: This paper presents a physic-based reverse short channel effect (RSCE) model for threshold voltage (Vth) modeling of deep submicron MOSFETs. Unlike those conventional empirically-based RSCE models, the proposed model is derived based on two Gaussian pile-up profiles located at the source and drain edges of a MOSFET. The model has a simple compact form that can be utilized to characterize the advanced halo-implant MOSFETs. A detailed comparison of the proposed RSCE model with the previously proposed model is also presented. The analytical model has been applied to, and verified with, experimental data of a 0.25-mm CMOS process for ten different gate lengths as well as various drain and substrate bias conditions.
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Applied Computational Research Society
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Journal of Modeling and Simulation of Microsystems, JMSM
ISSN# 1524-2021		 Vol. 1., No., 2.
Paper# 1/02765
Title: Multi-Level Digital/Mixed-Signal Simulation with Automatic Circuit Partition and Dynamic Delay Calculation
Author(s): T. Tang, X. Zhou
Affiliation: Department of Electrical Engineering, University of Rochester, Rochester, NY 14627, U.S.A.
Keywords: multi-level digital-/mixed-signal simulation, circuit partition, dynamic delay
Abstract: A unified and consistent representation of logic gates at logic and circuit levels is described based on the subcircuit expansion approach. A dynamic-delay model is proposed for gate-level timing simulation, which includes the effects of nonlinear capacitive loading, input transition time, and multiple-input triggering on the delay. It is shown that the approach provides near circuit-level accuracy with gate-level speed and is useful for accurate timing simulation of digital and mixed-signal VLSI circuits.
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© Computational Publications
Applied Computational Research Society
http://www.cr.org