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A general approach to compact threshold
voltage formulation based on 2D numerical simulation and experimental correlation
for deep-submicron ULSI technology development [CMOS]
- Xing Zhou;
Khee Yong Lim; Lim, D.
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
This Paper Appears in :
Electron Devices, IEEE Transactions on
on Pages: 214 - 221
Jan. 2000 |
Vol. 47 |
Issue: 1 |
ISSN: 0018-9383 |
References Cited: 12
CODEN: IETDAI
Accession Number: 6472173
Abstract:
A unified compact threshold voltage model
is developed, which accounts for the normal and reverse short-channel effects
with full range of body- and drain-bias conditions, and has been verified
with experimental data down to 0.18 /spl mu/m. The model only has five
process-dependent fitting parameters with a simple one-iteration extraction
procedure, and can be correlated to process variables for aiding new deep-submicron
technology development. The approach to the model formulation is original
and general, and can be extended to other key device performance parameters.
Subject Terms:
circuit simulation; threshold voltage formulation;
2D numerical simulation; deep-submicron ULSI technology; short-channel
effects; body-bias conditions; drain-bias conditions; process-dependent
fitting parameters; one-iteration extraction procedure; process variables;
model formulation; 0.18 micron
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