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MOSFET Compact I-V Modeling for Deep-Submicron Technology DevelopmentAbstract
A unified compact Ids model for deep-submicron (DSM) MOSFETs is developed. The model includes all major short-channel effects and covers full range of gate length (without "binning") and biases for a given technology, which requires minimum measurement data for parameter extraction following a prioritized two-iteration sequence. The fitting parameters all have their physical meanings and are extracted from a given technology, which can be correlated to true process variables for predicting process fluctuations on electrical performance and for aiding new technology development. The demonstrated approach to DSM MOSFET compact modeling represents a first step towards bridging technology developers and circuit designers.
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