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The Missing Link to Seamless SimulationAbstract
The trends and needs in multi-level modeling of ULSI systems are reviewed in the context of nanometer CMOS technology, with an emphasis from the model/tool developer’s perspective. A dual representation of transistors/circuits is proposed and demonstrated through physics-based transistor compact modeling and a single-engine circuit simulator. Extension to process correlation and block-level representation is also proposed, which will be the key to studying process effects on system performance. This consistent dual representation allows detailed physics captured at a lower level to be propagated to the higher level of abstraction. The key idea is to build a physics-based device compact model (CM) based on technology characterization, which serves as the building block for an implicit multi-level circuit simulator based on a subcircuit-expansion approach. In this way, process variation can be captured through device CMs, and its effects on circuit/system performance can be linked to a consistent hierarchy of abstractions within the same simulator engine.