Scalable Technology in the Nanoelectronics Era: Top-down versus Bottom-up
IV-2: Scalable Technology in the Nanoelectronics Era: Top-down versus Bottom-up |
||||||||
Dr Zhou Xing Microelectronics Division, School of EEE, NTU |
||||||||
Abstract |
||||||||
|
Traditional microelectronics has evolved into the nanoelectronics era with continued “top-down” technology scaling into the nanoscale regime of the intersection with emerging “bottom-up” nanotechnologies. While the latter is being explored with various prototypes, it is imperative to sustain the former in the mainframe CMOS scaling into non-classical alternatives. This calls for physics-based compact models that are scalable with length, width, depth dimensions as well as frequency and temperature, which can be used in top-down system/circuit/process designs. The proposed research aims at extending the ongoing SRC-sponsored project on predictive compact model development into the non-classical nanoscale CMOS of the future.
The 2004 IEDM evening panel discussion debated the question of what the intersection of “top-down” (traditional CMOS scaling) and “bottom-up” (emerging technologies at the molecular/atomistic level) electronics will mean to semiconductor technology of the future. In order to sustain top-down technology scaling in which lateral (length/width) dimensions are already in the nanometer scale, the depth dimension has been explored with various alternatives, such as hetero/layer-structured strained-Si/SiGe, fully/partially-depleted (FD/PD) and ultra-thin body (UTB) SOI, including gate/dielectric/source-drain extension engineering, as well as vertical-structured double-gate, tri-gate, gate-all-around FETs. A physical device model scalable in these dimensions is critical in analyzing and designing these future non-classical MOSFETs. Our ongoing bulk CMOS compact model development has been supported by Chartered since 1997 and recently sponsored by Semiconductor Research Corp (SRC) on “Technology-Based Predictive Compact Model Development for Next Generation CMOS”, which is currently joining in concert with Compact Model Council (CMC) call for next generation CMOS standard compact models with leading developments worldwide (including BSIM5 from UC Berkeley, PSP from Philips and PennState, HiSIM from Hiroshima, EKV from EPFL, etc.). We have already demonstrated single-piece DC/AC model that is predictive for 0.11-m technology using minimum measurement data, as well as extension to strained-Si MOSFETs and poly-gate accumulation/depletion/inversion and quantum-mechanical effects. Collaboration with IME on 45nm non-classical CMOS model development under A*STAR’s TSRP has also started. The proposed research is to extend the ongoing development into scalable RF regime with physical compact models built in (rather than user extracted subcircuit), as well as extending to heterostructure MOSFETs such as strained-Si and FD/PD UTB SOI. The ultimate goal is to develop a modeling infrastructure that is scalable and predictive for technology development and circuit design in the future non-classical devices and technology nodes. |
