Laser thermal processing for the formation of silicided nanojunctions in nanoelectronics

I-3: Reliability & interfacial characterization of breakdown in nano-gate stack structures
KL Pey School of EEE
Co-PI: CH Tung, IME Local collaborators: DS Ang, School of EEE, NTU L Bera, IME S. O’Shea, IMRE WH Lim, Chartered Semiconductor Manufacturing Overseas collaborators: G. Groeseneken, IMEC, Belgium S. Lombardo, IMM-CNR, Italy
Abstract
This project aims to extend the current physical analysis study on breakdown in ultra-thin gate dielectrics in nano-gate stack structures to the study of the change in the electronic structure, conduction and material properties and chemical composition of gate dielectric breakdown spot at atomic resolution. In the proposed approach, a nano-scale current-voltage characterization technique based on UHV conductive atomic force microscopy and scanning tunneling microscopy, and a ultra-high resolution monochromator transmission electron microscopy technique will be used to study the underlying mechanism(s) responsible for breakdown evolution in ultra-thin SiON- and high-based dielectrics used for nano-scale CMOS.
Laser thermal processing for the formation of silicided nanojunctions in nanoelectronics
KL Pey School of EEE
Local collaborators: PS Lee, School of EEE, NTU A Wee, NUS Wang Xincai and G.C Lim, SIMTech A Chong, Chartered Semiconductor Manufacturing Overseas collaborators: Peter Oesterlin, Innovavent GmbH, Germany Antonino La Magna, CNR, Italy
Abstract
The Excimer pulsed laser annealing (PLA) has become a promising technique for forming the nano-junctions for sub-45nm CMOS technologies. Our recent research has shown that by appropriate fine-tuning of a pre-amorphization implant (PAI), very abrupt 15-25nm p+/n- junction can be formed without much transient enhanced boron diffusion during the subsequent annealing. Melting of the PAI Si substrate is found to be a critical parameter. On the other hand, we demonstrate that non-melt laser annealing is critical in forming very abrupt nano-junctions in SOI and SiGe technology. CMOS narrow transistors with good electrical performance has been demonstrated using the developed non-conventional PLA technique.