Yu (family name) Hao (given name)

Assistant Professor 2009

School of Electrical and Electronic Engineering
Nanyang Technological University


S1-B1c-109
50 Nanyang Avenue, Singapore
Tel: 65+6790 4509
Fax: 65+6793 3318
email: haoyu at ntu dot edu dot sg


Please contact haoyu at ntu dot edu dot sg for further information such as Ph.D/Postdoc fellowship support.

Biography

Dr. Yu Hao obtained his B.S. degree from Fudan University (Shanghai China) in 1999, with 4-year first-prize Guanghua scholarship (top-2) and 1-year Samsung scholarship for the outstanding student in science and engineering (top-1). After selected by the mini-cuspea program conducted by Nobel laureate Prof. T.D. Lee, he spent some time in New York University, SUNY-Stony Brook, and obtained M.S./Ph. D degrees both from electrical engineering department at UCLA in 2006, in the field of the integrated circuit and embedded computing. He was a senior research staff at Berkeley Design Automation (BDA) till 2009, one of top-100 start-ups selected by Red-herrings at Silicon Valley. Dr. Yu Hao has about 30 major international publications [conference (22) and journal (9)], 2 best paper award nominations in design automation conference (DAC) and international conference of computer-aided-design (ICCAD), 4 US-patent applications in pending and 1 inventor award from Semiconductor research cooperation (SRC). He is the associate editor of Journal of low power electronics, reviewer of IEEE TCAS-I/II TCAD, TVLSI, ACM-TODAEs, VLSI Integration, and session chair of several conferences. His industry work at BDA is also recognized with an EDN magazine innovation award and multi-million-US$ venture capital fund.

Journals

J1. Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He and Sheldon X.D. Tan, "Fast Analysis of Large Scale Inductive Interconnect by Block Structure Preserved Macromodeling", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2009 (in press) (pdf)
J2. Hao Yu, Lei He, and M.C.Frank Chang, "Robust On-chip Signaling using Staggered and Twisted Interconnect", IEEE Design and Test of Computers (DTC), September 2009 (SRC inventor award 2008). (pdf)
J3. Hao Yu, Joanna Ho and Lei He, "Allocating Power Ground Vias in 3D ICs for Simultaneous Power and Thermal Integrity" ACM Transactions on Design Automation of Electronic Systems (TODAES), May 2009.(pdf)
J4. Hao Yu, Yiyu Shi, Lei He, and Tanay Karnik, "Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), December 2008. (pdf)
J5. Yiyu Shi, Paul Mesa, Hao Yu, and Lei He, "Circuit Simulated Obstacle-Aware Steiner Routing", ACM Transactions on Design Automation of Electronic Systems (TODAES), August 2007. (pdf)
J6. Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, and Lei He, "Wideband Passive Multi-Port Model Order Reduction and Realization of RLCM Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), August 2006. (pdf)
J7. Hao Yu, and Lei He, "A Provably Passive and Cost Efficient Model for Inductive Interconnects", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), August 2005. (pdf)
J8. Jens Jensen, R. Chandra, and Hao Yu, "Quantitative model for the Interecho Time Dependence of the CPMG Relaxation Rate in Iron-rich Gray Matter", Magnetic Resonance in Medicine, 46(1): 159-65, July 2001. (pdf)
J9. Chu-Shun Tian, Hao Yu, Chi Zhang, and Quan-Kang Lu, "The First Principle Calculation of Green-Kubo Formula with the Two-Time Ensemble Technique", Communications in Theoretical Physics, vol.35, no.04, 2001. (pdf)

Conferences

C1. Hao Yu, Lei He, and Sheldon.X.D. Tan, "Vector Potential Equivalent Circuit Based on PEEC Inversion", ACM/IEEE Design Automation Conference (DAC), June 2003. (pdf)
C2. Hao Yu, Lei He, Sheldon.X.D. Tan, "Macromodeling for RF Passives via Circuit Reduction of VPEC Model", IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, June 2004. (pdf)
C3. Hao Yu, Lei He, Zhenyu Qi, and Sheldon X.-D. Tan, "A Wideband Realizable Circuit-Reduction for RLCM Interconnects", IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2005. (pdf)
C4. Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, and Lei He, "Wideband Modeling of RF/Analog Circuits via Hierarchical Multi-Point Model Order Reduction", IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2005. (pdf)
C5. Hao Yu, and Lei He, "Analysis and Synthesis of Staggered Twisted Bundle for Crosstalk Reduction", IEEE/ACM International Symposium on Quality Electronic Design (ISQED), March 2005. (ps)
C6. Hao Yu, and Lei He, "A Sparsified Vector Potential Equivalent Circuit Model for Massively Coupled Interconnects", IEEE International Symposium on Circuits and Systems (ISCAS), May 2005. (pdf)
C7. Hao Yu, Lei He, and Sheldon X.-D. Tan, "Block Structure Preserving Model Order Reduction", IEEE International Behavioral Modeling and Simulation Conference (BMAS), September 2005. (pdf)
C8. Yiyu Shi, Hao Yu, and Lei He, "SAMSON: Generalized Second-Order Arnoldi Method for Model Order Reduction with Multiple Non-impulse Sources", ACM International Symposium on Physical Design (ISPD), April 2006. (pdf)
C9. Hao Yu, Yiyu Shi, and Lei He, "Fast Analysis of Structured Power Grid by Triangularization Based Structure Preserving Model Order Reduction", ACM/IEEE Design Automation Conference (DAC) (Best Paper Award Nomination) , July 2006. (pdf)
C10. Yiyu Shi, Paul Mesa, Hao Yu, and Lei He, "Circuit Simulation Based Obstacle-aware Steiner Routing", ACM/IEEE Design Automation Conference (DAC), July 2006. (pdf)
C11. Hao Yu, Yiyu Shi, Lei He, and Tanay Karnik "Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power", ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), October 2006. (pdf)
C12. Hao Yu, Joanna Ho, and Lei He, "Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs", IEEE/ACM International Conference of Computer-Aided-Design (ICCAD) (Best Paper Award Nomination) , November 2006. (pdf)
C13. Hao Yu, Yiyu Shi, Lei He and David Smart, "A Fast Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits", IEEE/ACM International Conference of Computer-Aided-Design (ICCAD), November 2006. (pdf)
C14. Hao Yu, Yu Hu, Chuenchen Liu, and Lei He, "Minimal Skew Clock Embedding Considering Time Variant Temperature Variation with Automatic Correlation Extraction", ACM International Symposium on Physical Design (ISPD), March 2007. (pdf)
C15. Ning Mi, Boyuan Yan, Sheldon X.-D. Tan, and Hao Yu, "General block structure-preserving reduced order modeling of interconnect circuits", IEEE/ACM International Symposium. on Quality Electronic Design (ISQED), March 2007. (pdf)
C16. Hao Yu, Chunta Chu, and Lei He, "Off-chip Decoupling Capacitor Allocation for Chip Package CoDesign", ACM/IEEE Design Automation Conference (DAC), July 2007. (pdf)
C17. Hai Wang, Hao Yu, and Sheldon X.D. Tan, "Fast Clock Skew Analysis Considering Environmental Uncertainty by Parameterized and Incremental Macro-models", IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2009. (pdf)
C18. Hao Yu, and Lei He, "Dynamic power and thermal integrity in 3D integration", IEEE International Conf. of Communication, Circuit and System (ICCCAS), July 2009 (Invited). (pdf)
C19. Fang Gong, Hao Yu, and Lei He, "Picap: a parallel and incremental full-chip capacitance extraction considering random process variation ", ACM/IEEE Design Automation Conference (DAC), July 2009. (pdf)
C20. Hao Yu, and Sheldon X.D. Tan, "Recent Advance in Computational Prototyping for Analysis of High-performance Analog/RF ICs", IEEE International Conf. on ASIC (ASICON), October 2009 (Invited).
C21. Hao Yu, Xuexin Liu, Hai Wang and Sheldon X.D. Tan, "A Fast Analog Mismatch Analysis by an Incremental and Stochastic Trajectory Piecewise Linear Macromodel", IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2010. (pdf)
C22. Hao Yu, and Wei Fei, "A New Modified Nodal Analysis for Nano-Scale Memristor Circuit Simulation", IEEE International Symposium on Circuits and Systems (ISCAS), May 2010. (to appear)


Copyrights are owned by the publisher. PS/PDF files here are provided as a convenience for one-time individual use.

Patents

P1. Lei He and Hao Yu, "Structured and Parameterized Model Order Reduction", US Patent Office, filed 2006.
P2. Lei He and Hao Yu, "On-chip Staggered and Twisited Bundles for Crosstalk Reduction", US Patent Office, filed 2006.
Two more undisclosed.

Talks

T1. Hao Yu, "Structured and Parameterized Macromodeling for High Performance Mixed-mode System Integration", Ph.D. Forum at ACM/IEEE Design Automation Conference, July 2006, Defense Talk at UCLA, December 2006, Invited Talk at UC-Riverside, Feburary 2007. (pdf)

Last Updated 10/15/2009

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