PEY Kin Leong
Visiting Professor of School of Electrical & Electronic Engineering
Division of Microelectronics



Phone: (65) 6790 6371, Fax: (65) 6792 0415
Office: S2-B2b-67
Email: peykinleong@su.edu.sg
Personal WebSite:www.ntu.edu.sg/home/eklpey/

Biography

Dr. PEY Kin Leong received his Bachelor of Engineering (1989) and Ph.D (1994) in Electrical Engineering from the National University of Singapore. He has held various research positions in the Institute of Microelectronics, Chartered Semiconductor Manufacturing, Agilent Technologies and National University of Singapore. He is currently a Full Professor, Head of the Microelectronics Division, Program Director of the Si Technology Research group, Laboratory Supervisor of the MicroFabrication Facility, and the Director of the Microelectronic Center in the School of Electrical & Electronics Engineering, Nanyang Technological University, Singapore, and holds a concurrent Fellowship appointment in the Singapore-MIT Alliance (SMA).
Dr. Pey is a senior member of IEEE and an IEEE EDS Distinguished Lecturer, and has been the organizing committee member of IPFA since 1995. He was the General Chair of IPFA2001, Singapore and the co-General Chair of IPFA2004, Hsinchu, Taiwan. KL Pey was the Guest Editor of IEEE Transactions on Devices in and Materials Reliability in 2003-05 and 2007, and the Chair of the Singapore IEEE REL/CPMT/ED Chapter in 2004/05, and served on the 2006/07/08 IRPS technical subcommittee, and the IPFA’02 to IPFA’06 and IPFA’08 technical committee, and the 2007 IEDM CMOS & Interconnect Reliability and 2008 IEDM Characterization, Reliability and Yield sub-committee.
Dr. Pey has published more than 130 international refereed publications (including 4 invited papers and one review article) and 140 technical papers at international meetings/conferences (including 21 invited talks and 17 papers in IEDM/IRPS), and holds 33 US patents. Dr. Pey has published 8 papers in the World’s premier Device conference, IEEE Electron Device Meeting, since 2001 and the IEDM paper in 2008 has been selected as a highlight. Dr. Pey has contributed significantly to the CMOS gate dielectric reliability, especially in the areas of physical analysis of ultrathin dielectric breakdown mechanism. Two of his graduate students working in gate dielectric reliability have recently received the 2008 TSMC Outstanding Student Research Awards. Dr. Pey's research interests are pulsed laser annealing for channel engineering for nano-scale CMOS, advanced alloy silicide for nanostructures and nanodevices, and transistor reliability in dielectric breakdown and advanced interconnects.

Research Interest

Pulsed laser annealing for channel engineering for nano-scale CMOS, advanced alloy silicide for nanostructures and nanodevices, and device and transistor reliability in dielectric breakdown and advanced interconnects.

Selected Research Projects

  • PI of A*STAR Public Sector Fund, “Pulsed laser annealing for the formation of alloy silicides and ultra-shallow junctions for advanced semiconductor technology”, S$249,000, 1 Oct 2003 – 30 Sep 2006.
  • Co-PI of A*STAR TSRP on Nanoelectronics – the next wave, “Scanning Probe Methods to Investigate the Performance of Nanoelectronic Devices, Interfaces and Materials”, S$1.3107M, 1 Oct 2004 – 30 Sep 2007.
  • Co-PI of A*STAR TSRP on Nanoelectronics – the next wave, “Developing New Germanosilicide/Germanide Materials and Processes for Future Nano-scale MOSFET Devices”, S$878,194, 1 Oct 2004 – 30 Sep 2007.

Selected Publications

  • R. Ranjan, K.L. Pey, C.H. Tung, D.S. Ang, L.J. Tang, T. Kauerauf, R. Degraeve, G. Groeseneken, S. De Gendt and L.K. Bera, “ Ultrafast progressive breakdown associated with metal-like filament formation of breakdown path in HfO 2/TaN/TiN transistor”, Applied Physics Letters, Vol. 88, pg. 122907, 2006.
  • E.J. Tan, Mathieu Bouville, Dong Zhi Chi, KL Pey, PS Lee, David J. Srolovitz, and Chih Hang Tung, “Pyramidal structural defects in erbium silicide thin films”, Applied Physics Letters, Vol. 88, pg. 021908, 2006.
  • E.J. Tan, K.L. Pey, D.Z. Chi, P.S. Lee, and L.J. Tang, “Improved electrical performance of erbium silicide Schottky diodes formed by pre-RTA amorphization of Si”, IEEE Electronic Device Letters, Vol. 27, no. 2, Feb 2006, pp. 93-95.
  • R Ranjan, KL Pey, CH Tung, LJ Tang, G Groeseneken, LK Bera and S De Gendt, “ A Comprehensive Model for Breakdown Mechanism in HfO 2 High- k Gate Stacks”, IEEE IEDM Tech. Dig., pp. 725 - 728, 2004.
  • KL Pey , VL Lo, CH Tung, W Chandra, LJ Tang, DS Ang, R Ranjan, “New insight into gate dielectric breakdown induced MOSFET degradation by novel percolation path resistance measurements”, IEEE IEDM Tech. Dig., pp. 717 - 720, 2004.