YU Hong Yu
Nanyang Assistant Professor of School of Electrical & Electronic Engineering
Division of Microelectronics



Phone: (65) 6790 4360, Fax: (65) 6792 0415
Office: S2.2-B2-45
Email: HYYU@ntu.edu.sg

Biography

Hong Yu Yu received the B.Eng. degree from Tsinghua University, Beijing, China, the M.A.Sc. degree from the University of Toronto, Toronto, ON, Canada, and the Ph.D. degree from the National University of Singapore, Singapore. From 2004.06 to 2008.01, he was with the R&D Division of IMEC, Belgium, as a senior researcher. He joined school of EEE, NTU as an assistant professor starting from 2008.01.
He has authored or coauthored more than 120 papers in referred technical journals and conference proceedings in the area of semiconductor physics and fabrication, including 18 IEDM/VLSI, >30 letters (EDL & APL), and several invited papers. He also has > 15 U.S. patents published or being published. He is a recipient of NUS president fellowship (2003) and IEEE Electron Device Society graduate fellowship (2004).

Research Interest

Emerging Si-based Nano Electronic Device in the areas of both “More Moore” and “More than Moore”
1) Novel Non-Volatile Memory Research
2) Sub-22nm CMOS devices based on high-mobility substrates
3) SiGe based Nano-wire devices
4) Advanced Photovoltaic devices
5) CMOS photonics

Selected Research Projects


Teaching

  • Semiconductor Device Physics and Process Technology

Selected Publications

  • H.Y. Yu, et. al, “Energy Gap and Band Alignment for (HfO2)x(Al2O3)1-x on (100) Si”, Applied Physics Letter, vol. 81, pp. 376–378, July, 2002
  • H.Y. Yu, et. al, “Thermally Robust HfN Metal as a Promising Gate Electrode for Advanced MOS Device Application,” IEEE Transaction on Electron Devices, vol. 51, pp. 609-615, Apr., 2004
  • H.Y. Yu, et. al, “Fermi Pinning Induced Thermal Instability of Metal Gate Work Functions,” IEEE Electron Device Letter, vol. 25, pp. 337-379, May, 2004
  • (Highlight paper) H.Y. Yu, et.al, “Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases,” IEEE Sym. VLSI Tech. 2007, Kyoto, Japan
  • (Invited) H.Y. Yu, et. al., “Advanced Gate Stack technology for sub-45nm CMOS devices”, 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Oct., 2008, Beijing, China